 | 2012 |
|---|
| 19 |       | Bernhard Fechner,
Arne Garbade,
Sebastian Weis,
Theo Ungerer:
Fault Localization in NoCs by Timed Heartbeats.
ARCS Workshops 2012: 191-200 |
| 18 |  | Bernhard Fechner:
A multilevel fault model for integrated parallel fault-tolerant systems.
Concurrency and Computation: Practice and Experience 24(7): 687-698 (2012) |
| 17 | | Bernhard Fechner:
3, 14159... oder die näherungsweise Berechnung von π.
Informatik Spektrum 35(3): 215-219 (2012) |
| 2010 |
|---|
| 16 | | Bernhard Fechner:
GPU-Based Parallel Signature Scanning and Hash Generation.
ARCS Workshops 2010: 133-138 |
| 15 | | Bernhard Fechner,
Andre Osterloh:
A meta-level true random number generator.
IJCCBS 1(1/2/3): 267-279 (2010) |
| 2009 |
|---|
| 14 | | Bernhard Fechner:
Transiente Fehler in Mikroprozessoren: Mechanismen zur Erkennung, Behebung und Tolerierung.
FernUniversität in Hagen 2009: 1-265 |
| 2008 |
|---|
| 13 | | Bernhard Fechner,
Andre Osterloh:
A True Random Number Generator with Built-in Attack Detection.
DepCoS-RELCOMEX 2008: 111-118 |
| 12 | | Bernhard Fechner,
Udo Hönig,
Jörg Keller,
Wolfram Schiffmann:
Fault-tolerant static scheduling for grids.
IPDPS 2008: 1-6 |
| 11 | | Bernhard Fechner:
Dynamische Fehlererkennungs- und behebungsmechanismen für verlässliche Mikroprozessoren.
FernUniversität in Hagen 2008: 1-187 |
| 2007 |
|---|
| 10 | | Bernhard Fechner,
Andre Osterloh:
Transient Fault Detection in State-Automata.
DepCoS-RELCOMEX 2007: 99-106 |
| 2006 |
|---|
| 9 | | Bernhard Fechner:
Microcode with Embedded Timing Constraints.
ARCS Workshops 2006: 45-51 |
| 8 | | Bernhard Fechner:
Analysis of checksum-based execution schemes for pipelined processors.
IPDPS 2006 |
| 7 | | Bernhard Fechner,
Jörg Keller,
Andreas Wohlfeld:
Web server protection by customized instruction set encoding.
IPDPS 2006 |
| 6 | | Bernhard Fechner:
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.
PARELEC 2006: 31-36 |
| 5 | | Bernhard Fechner:
A Result Propagation Scheme for Redundant Multithreaded Systems.
PDPTA 2006: 64-69 |
| 2005 |
|---|
| 4 | | Irene Eusgeld,
Bernhard Fechner,
Felix Salfner,
Max Walter,
Philipp Limbourg,
Lijun Zhang:
Hardware Reliability.
Dependability Metrics 2005: 59-103 |
| 3 | | Bernhard Fechner:
Dynamic Delay-Fault Injection for Reconfigurable Hardware.
IPDPS 2005 |
| 2004 |
|---|
| 2 | | Bernhard Fechner,
Jörg Keller,
Peter Sobe:
Performance Estimation of Virtual Duplex Systems on Simultaneous Multithreaded Processors.
IPDPS 2004 |
| 1 | | Bernhard Fechner,
Jörg Keller:
A Fault-Tolerant Voting Scheme for Multithreaded Environments.
PARELEC 2004: 237-239 |
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