| | |
- CSB - MetaPress - Google - Bing - Yahoo
 | 2009 | |
|---|---|---|
| 2 |      | Kaleem Fatima, Rameshwar Rao: A New Hardware Routing Accelerator for Multi-Terminal Nets. VLSI Design 2009: 393-398 |
| 2007 | ||
| 1 | | Kaleem Fatima, Vijay Gopal Sarvepalli, Zeeshan Nadeem Nakhi: A Novel Architecture for the Computation of the 2D-DWT. CIS 2007: 531-535 |
| 1 | Zeeshan Nadeem Nakhi | [1] |
| 2 | Rameshwar Rao | [2] |
| 3 | Vijay Gopal Sarvepalli | [1] |
Colors in the list of coauthors
Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —
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