Shan Chien Fang

	2009
3		Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang: Design Optimization and Automation for Secure Cryptographic Circuits. VLSI Design 2009: 321-326
	2007
2		Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo: Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. DATE 2007: 1265-1270
	2006
1		Kuan Jen Lin, Shih Hao Huang, Shan Chien Fang: Cooptimization of interface hardware and software for I/O controllers. DATE 2006: 724-725

Coauthor Index

1	Yi Tang Chiu	[3]
2	Shih Hao Huang	[1]
3	Kuan Jen Lin	[1] [2] [3]
4	Cheng Chia Lo	[2]
5	Shih Hsien Yang	[2]

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