Marius Evers

	2007
9		Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari: Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ISPD 2007: 67-74
	1998
8		Jared Stark, Marius Evers, Yale N. Patt: Variable Length Path Branch Prediction. ASPLOS 1998: 170-179
7		Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271
6		Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61
5		Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. International Journal of Parallel Programming 26(4): 449-478 (1998)
	1997
4		Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997)
3		Po-Yung Chang, Marius Evers, Yale N. Patt: Improving branch prediction accuracy by reducing pattern history table interference. International Journal of Parallel Programming 25(5): 339-362 (1997)
	1996
2		Marius Evers, Po-Yung Chang, Yale N. Patt: Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA 1996: 3-11
1		Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO 1996: 191-200

Coauthor Index

1	Po-Yung Chang	[1] [2] [3] [5]
2	Robert S. Chappell	[6]
3	Daniel H. Friendly	[4]
4	Alper Halbutogullari	[9]
5	Eric Hao	[1] [5]
6	Sanjay J. Patel	[4] [6] [7]
7	Yale N. Patt	[1] [2] [3] [4] [5] [6] [7] [8]
8	Jeegar Tilak Shah	[9]
9	Jared Stark	[4] [8]
10	Jeff Trull	[9]

Colors in the list of coauthors

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