 | 2012 |
| 11 |  | Shailendra Jain,
Surhud Khare,
Satish Yada,
V. Ambili,
Praveen Salihundam,
Shiva Ramani,
Sriram Muthukumar,
M. Srinivasan,
Arun Kumar,
Shasi Kumar,
Rajaraman Ramanarayanan,
Vasantha Erraguntla,
Jason Howard,
Sriram R. Vangal,
Saurabh Dighe,
Gregory Ruhl,
Paolo A. Aseron,
Howard Wilson,
Nitin Borkar,
Vivek De,
Shekhar Borkar:
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.
ISSCC 2012: 66-68 |
| 10 |  | Praveen Salihundam,
Mohammed Asadullah Khan,
Shailendra Jain,
Yatin Hoskote,
Satish Yada,
Shasi Kumar,
Vasantha Erraguntla,
Sriram R. Vangal,
Nitin Borkar:
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
VLSI Design 2012: 292-297 |
| 2011 |
| 9 |  | Jason Howard,
Saurabh Dighe,
Sriram R. Vangal,
Gregory Ruhl,
Nitin Borkar,
Shailendra Jain,
Vasantha Erraguntla,
Michael Konow,
Michael Riepen,
Matthias Gries,
Guido Droege,
Tor Lund-Larsen,
Sebastian Steibl,
Shekhar Borkar,
Vivek K. De,
Rob F. Van der Wijngaart:
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
J. Solid-State Circuits 46(1): 173-183 (2011) |
| 8 |  | Saurabh Dighe,
Sriram R. Vangal,
Paolo A. Aseron,
Shasi Kumar,
Tiju Jacob,
Keith A. Bowman,
Jason Howard,
James Tschanz,
Vasantha Erraguntla,
Nitin Borkar,
Vivek K. De,
Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
J. Solid-State Circuits 46(1): 184-193 (2011) |
| 7 |  | Praveen Salihundam,
Shailendra Jain,
Tiju Jacob,
Shasi Kumar,
Vasantha Erraguntla,
Yatin Hoskote,
Sriram R. Vangal,
Gregory Ruhl,
Nitin Borkar:
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
J. Solid-State Circuits 46(4): 757-766 (2011) |
| 2010 |
| 6 |  | Jason Howard,
Saurabh Dighe,
Yatin Hoskote,
Sriram R. Vangal,
David Finan,
Gregory Ruhl,
David Jenkins,
Howard Wilson,
Nitin Borkar,
Gerhard Schrom,
Fabric Pailet,
Shailendra Jain,
Tiju Jacob,
Satish Yada,
Sraven Marella,
Praveen Salihundam,
Vasantha Erraguntla,
Michael Konow,
Michael Riepen,
Guido Droege,
Joerg Lindemann,
Matthias Gries,
Thomas Apel,
Kersten Henriss,
Tor Lund-Larsen,
Sebastian Steibl,
Shekhar Borkar,
Vivek De,
Rob F. Van der Wijngaart,
Timothy G. Mattson:
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.
ISSCC 2010: 108-109 |
| 5 |  | Saurabh Dighe,
Sriram R. Vangal,
Paolo A. Aseron,
Shasi Kumar,
Tiju Jacob,
Keith A. Bowman,
Jason Howard,
James Tschanz,
Vasantha Erraguntla,
Nitin Borkar,
Vivek De,
Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
ISSCC 2010: 174-175 |
| 4 |  | Shailendra Jain,
Vasantha Erraguntla,
Sriram R. Vangal,
Yatin Hoskote,
Nitin Borkar,
Tulasi Mandepudi,
V. P. Karthik:
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.
VLSI Design 2010: 252-257 |
| 2009 |
| 3 |  | Suresh Srinivasan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
VLSI Design 2009: 301-306 |
| 2008 |
| 2 |  | Rajaraman Ramanarayanan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy,
Shay Gueron:
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
VLSI Design 2008: 273-278 |
| 2004 |
| 1 |  | Siva Narendra,
Vasantha Erraguntla,
James Tschanz,
Nitin Borkar:
Design Challenges in Sub-100nm High Performance Microprocessors.
VLSI Design 2004: 15-17 |