Luis Entrena

Luis Entrena-Arrontes

	2012
49		Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil: Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. IEEE Trans. Computers 61(3): 313-322 (2012)
	2011
48		Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena: Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS 2011: 179-181
47		Honorio Martin, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez: AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS 2011: 228-233
46		Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena: Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. IOLTS 2011: 258-263
45		Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena: Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. IEEE Trans. Dependable Sec. Comput. 8(2): 308-314 (2011)
	2010
44		Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena: An on-line fault detection technique based on embedded debug features. IOLTS 2010: 167-172
43		Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena: Robust cryptographic ciphers with on-line statistical properties validation. IOLTS 2010: 208-210
	2009
42		Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena: In-depth analysis of digital circuits against soft errors for selective hardening. IOLTS 2009: 144-149
41		Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena: Briefing power/reliability optimization in embedded software design. IOLTS 2009: 185-186
40		Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena: Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS 2009: 203-205
39		Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García: SET Emulation Under a Quantized Delay Model. J. Electronic Testing 25(1): 107-116 (2009)
	2008
38		Enrique San Millán, Luis Entrena, José Alberto Espejo: Logic Transformations by Multiple Wire Network Addition. DSD 2008: 779-786
37		Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez: Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. FPL 2008: 539-542
36		Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena: Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS 2008: 167-168
	2007
35		Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez: Wavelet-Based Fingerprint Region Selection. CAIP 2007: 391-398
34		Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena: SET Emulation Under a Quantized Delay Model. DFT 2007: 68-77
33		Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán: Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721
32		Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena: A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS 2007: 101-106
31		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation CoRR abs/0710.4757: (2007)
30		Almudena Lindoso, Luis Entrena: High performance FPGA-based image correlation. J. Real-Time Image Processing 2(4): 223-233 (2007)
29		Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena: Low power data processing system with self-reconfigurable architecture. Journal of Systems Architecture 53(9): 568-576 (2007)
	2006
28		Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes: An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS 2006: 218-219
27		Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82
26		Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena: Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS 2006: 183-184
	2005
25		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. DATE 2005: 308-309
24		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. FPL 2005: 397-402
23		Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez: Correlation-Based Fingerprint Matching Using FPGAs. FPT 2005: 87-94
22		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. IOLTS 2005: 43-48
	2004
21		Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena: Architectures for Biometric Match-on-Token Solutions. ECCV Workshop BioAW 2004: 195-204
20		Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena: FPGA Implementation of Biometric Authentication System Based on Hand Geometry. FPL 2004: 43-53
19		Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena: Power Consumption Reduction Through Dynamic Reconfiguration. FPL 2004: 751-760
18		Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena: Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS 2004: 109-114
	2003
17		Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo: Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. FPL 2003: 220-229
16		Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo: State Encoding for Low-Power FSMs in FPGA. PATMOS 2003: 31-40
15		Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López: Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. Journal of Systems Architecture 49(12-15): 529-541 (2003)
	2002
14		Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López: New Techniques for Speeding-Up Fault-Injection Campaigns. DATE 2002: 847-852
13		Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero: Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW 2002: 193
12		Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López: An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS 2002: 229-236
	2001
11		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472
10		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397
9		Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299
8		Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94
7		Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo: Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
6		Luis Entrena, Celia López, Emilio Olías: Automatic Insertion of Fault-Tolerant Structures at the RT Level. IOLTW 2001: 48-50
	1999
5		Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno: Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520
4		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161-
	1995
3		Serafín Olcoz, Luis Entrena, Luis Berrojo: An effective system development environment based on VHDL prototyping. EURO-DAC 1995: 502-507
2		Luis Entrena-Arrontes, Kwang-Ting Cheng: Combinational and sequential logic optimization by redundancy addition and removal. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 909-916 (1995)
	1993
1		Luis Entrena, Kwang-Ting Cheng: Sequential logic optimization by redundancy addition and removal. ICCAD 1993: 310-315

Coauthor Index

1	Luis Berrojo	[3] [12] [13] [14]
2	Raúl Fernández Cardenal	[34] [39] [49]
3	Fernando Casado	[20]
4	Julio César Hernández Castro (Julio C. Hernandez-Castro)	[47]
5	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[1] [2]
6	Silvia Chiusano	[5]
7	Fulvio Corno	[5] [12] [13] [14]
8	José Alberto Espejo	[4] [5] [7] [8] [9] [10] [11] [15] [38]
9	Mario García-Valderas	[18] [19] [22] [24] [25] [26] [28] [31] [32] [34] [36] [39] [40] [41] [42] [44] [45] [46] [49]
10	Isabel González	[12] [13] [14]
11	Michelangelo Grosso	[44]
12	Juan Izquierdo	[37]
13	Alejandro Jiménez-Horas	[36] [40] [43] [48]
14	Almudena Lindoso	[23] [30] [33] [35] [37] [49]
15	Judith Liu-Jimenez	[20] [21] [23] [33] [35] [37]
16	Celia López-Ongil (Celia López)	[6] [7] [12] [13] [14] [15] [18] [20] [22] [23] [24] [25] [26] [27] [28] [31] [32] [34] [36] [39] [40] [41] [42] [43] [44] [45] [46] [48] [49]
17	Michael G. Lorenz	[16] [17] [19] [29]
18	Honorio Martin	[47]
19	Luis Mengibar	[16] [17] [19] [29]
20	Enrique San Millán	[4] [5] [7] [8] [9] [10] [11] [15] [29] [33] [36] [38] [40] [43] [47] [48]
21	Serafín Olcoz	[3]
22	Emilio Olías	[4] [6] [7] [10] [11]
23	Pedro Peris-Lopez	[47]
24	Bernardo Pianta	[41]
25	Marta Portela-García	[18] [22] [24] [25] [26] [27] [28] [31] [32] [34] [36] [39] [40] [41] [42] [44] [45] [46] [49]
26	Matteo Sonza Reorda	[12] [13] [14] [27] [44]
27	Claudia A. Rocha	[41]
28	Leslie Sánchez	[20]
29	Raul Sánchez-Reillo	[16] [17] [20] [21]
30	Giovanni Squillero	[12] [13] [14]
31	Luca Sterpone	[27]
32	Fabian Vargas	[41]
33	Anna Vaskova	[43] [46] [48]
34	Massimo Violante	[27]

Colors in the list of coauthors

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page