Tom English

	2011
7		Tom English, Emanuel M. Popovici: Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators. NOCS 2011: 225-232
6		Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici: Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits. J. Low Power Electronics 7(3): 364-380 (2011)
5		Tom English, Emanuel M. Popovici, Maurice Keller, William P. Marnane: Network-on-Chip interconnect for pairing-based cryptographic IP cores. Journal of Systems Architecture - Embedded Systems Design 57(1): 95-108 (2011)
	2010
4		Rashmi Mehrotra, Tom English, Emanuel M. Popovici, Michel P. Schellekens: Delay dependent power optimisation of combinational circuits using AND-Inverter graphs. SoCC 2010: 9-14
	2009
3		Tom English, Ka Lok Man, Emanuel M. Popovici: BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation. PATMOS 2009: 216-226
2		Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane: A low-power pairing-based cryptographic accelerator for embedded security applications. SoCC 2009: 369-372
	2008
1		Tom English, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens: HotSpot: Visualizing dynamic power consumption in RTL designs. EWDTS 2008: 45-48

Coauthor Index

1	Steve Hollands	[6]
2	Maurice Keller	[2] [5]
3	Ka Lok Man (Ka L. Man)	[1] [2] [3]
4	William P. Marnane (Liam Marnane)	[2] [5]
5	Rashmi Mehrotra	[4] [6]
6	Emanuel M. Popovici	[1] [2] [3] [4] [5] [6] [7]
7	Michel P. Schellekens	[1] [2] [4] [6]

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