Piet Engelke

	2010
21		Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. International Journal of Parallel Programming 38(3-4): 185-202 (2010)
	2009
20		Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190
19		Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232
18		Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker: An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26
17		Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian: SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4): (2009)
	2008
16		Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker: Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633
15		Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen: Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266
14		Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker: A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. European Test Symposium 2008: 113-118
13		Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10
12		Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186
11		Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
	2006
10		Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. VLSI Syst. 14(2): 193-202 (2006)
9		Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006)
8		Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006)
	2005
7		Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271
6		Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348
5		Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005)
	2004
4		Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker: X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451
3		Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178
	2003
2		Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059
	2002
1		Ilia Polian, Piet Engelke, Bernd Becker: Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. ISMVL 2002: 216-

Coauthor Index

1	Bernd Becker	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
2	Bettina Braitling	[17]
3	Wu-Tung Cheng	[12] [13]
4	Mariane Comte	[14] [18]
5	Alejandro Czutro	[14] [18] [19] [20] [21]
6	Jean Marc Gallière	[6]
7	Friedrich Hapke	[4] [10]
8	Stefan Hillebrecht	[13]
9	Nicolas Houarche	[14] [18]
10	Seiji Kajihara	[15]
11	Martin Keim	[12] [13]
12	Sandip Kundu	[6] [7] [11]
13	Matthew D. T. Lewis	[19] [21]
14	Kohei Miyase	[15]
15	Yusuke Nakamura	[15]
16	Ilia Polian	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
17	Sudhakar M. Reddy	[19] [20] [21]
18	Michel Renovell	[2] [3] [5] [6] [8] [9] [11] [14] [17] [18]
19	Jürgen Schlöffel	[10] [16] [17]
20	Bharath Seshadri	[3] [11]
21	Stefan Spinner	[12] [15]
22	Yuyi Tang	[4] [10]
23	Harald P. E. Vranken	[4]
24	Xiaoqing Wen	[15]
25	Michael Wittke	[4] [10]
26	Hans-Joachim Wunderlich	[4] [10]

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