Amr Elshazly

	2012
13		Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154
12		Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu: A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC 2012: 242-244
11		Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu: A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC 2012: 464-466
	2011
10		Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu: A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154
9		Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu: A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC 2011: 438-450
8		Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu: A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC 2011: 440-442
7		Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu: A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC 2011: 92-94
6		Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu: A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. J. Solid-State Circuits 46(12): 2759-2771 (2011)
5		Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu: A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. J. Solid-State Circuits 46(12): 3150-3162 (2011)
4		Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu: A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. J. Solid-State Circuits 46(12): 3163-3173 (2011)
3		Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu: A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. J. Solid-State Circuits 46(8): 1870-1880 (2011)
	2010
2		Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu: A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC 2010: 1-4
	2006
1		Amr Elshazly, Khaled M. Sharaf: 2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing. ISCAS 2006

Coauthor Index

1	Pavan Kumar Hanumolu	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
2	Rajesh Inti	[3] [4] [5] [6] [7] [8] [9] [10] [12] [13]
3	Marcel A. Kossel	[10]
4	Sunwoo Kwon	[2]
5	Sachin Rao	[11] [13]
6	Karthikeyan Reddy	[13]
7	Naga Sasidhar	[5] [9]
8	Khaled M. Sharaf	[1]
9	Mrunmay Talegaonkar	[4] [13]
10	Thomas Toifl	[10]
11	Wenjing Yin	[3] [4] [5] [6] [7] [8] [9] [10]
12	Brian Young	[2] [3] [4] [6] [7] [10] [11] [12] [13]

Colors in the list of coauthors

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page