Gary Ellis

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2003

2 Bing Lu, Jiang Hu, Gary Ellis, Haihua Su: Process variation aware clock tree routing. ISPD 2003: 174-181

1997

1 Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273

	2003
2		Bing Lu, Jiang Hu, Gary Ellis, Haihua Su: Process variation aware clock tree routing. ISPD 2003: 174-181
	1997
1		Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273

Coauthor Index

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —

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1	Jiang Hu	[2]
2	Bing Lu	[2]
3	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[1]
4	Rob A. Rutenbar	[1]
5	Haihua Su	[2]