Yacoub M. El-Ziq

	1992
13		Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq: An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. ITC 1992: 382-388
	1990
12		Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq: A Hardware Accelerator for Maze Routing. IEEE Trans. Computers 39(1): 141-145 (1990)
	1987
11		Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq: A Hardware Accelerator for Maze Routing. DAC 1987: 800-806
	1984
10		Yacoub M. El-Ziq, Hamid H. Butt: Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. ITC 1984: 338-349
	1983
9		Yacoub M. El-Ziq, Hamid H. Butt: A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis. ITC 1983: 269-274
	1982
8		Yacoub M. El-Ziq, Stephen Y. H. Su: Fault Diagnosis of MOS Combinational Networks. IEEE Trans. Computers 31(2): 129-139 (1982)
	1981
7		Yacoub M. El-Ziq: Automatic test generation for stuck-open faults in CMOS VLSI. DAC 1981: 347-354
6		Yacoub M. El-Ziq, Richard J. Cloutier: Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI. ITC 1981: 536-546
	1980
5		Yacoub M. El-Ziq: A new test pattern generation system. DAC 1980: 62-68
	1979
4		Yacoub M. El-Ziq: Testing of MOS combinational networks a procedure for efficient fault simulation and test generation. DAC 1979: 162-170
	1978
3		Yacoub M. El-Ziq: Logic design automation of MOS combinational networks with fan-in, fan-out constraints. DAC 1978: 240-249
2		Yacoub M. El-Ziq, Stephen Y. H. Su: Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. IEEE Trans. Computers 27(10): 911-923 (1978)
	1977
1		Yacoub M. El-Ziq, Stephen Y. H. Su: Logic design automation of diagnosable MOS combinational logic networks. DAC 1977: 205-215

Coauthor Index

1	Hamid H. Butt	[9] [10]
2	Richard J. Cloutier	[6]
3	Wei-Cheng Her	[13]
4	Lin-Ming Jin	[13]
5	Sartaj Sahni (Sartaj K. Sahni)	[11] [12]
6	Stephen Y. H. Su	[1] [2] [8]
7	Youngju Won	[11] [12]

Colors in the list of coauthors

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