Richard J. Eickemeyer

	2011
13		Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer: Abstraction and microarchitecture scaling in early-stage power modeling. HPCA 2011: 394-405
	2005
12		Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA 2005: 238-242
11		Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner: POWER5 system microarchitecture. IBM Journal of Research and Development 49(4-5): 505-522 (2005)
10		Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel: Characterization of simultaneous multithreading (SMT) efficiency in POWER5. IBM Journal of Research and Development 49(4-5): 555-564 (2005)
	2000
9		Steven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O'Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, Larry D. Whitley: A performance methodology for commercial servers. IBM Journal of Research and Development 44(6): 851-872 (2000)
8		John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel: A multithreaded PowerPC processor for commercial servers. IBM Journal of Research and Development 44(6): 885-898 (2000)
	1997
7		Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lim, Mark S. Squillante, Ching-Farn Eric Wu: Evaluation of Multithreaded Processors and Thread-Switch Policies. ISHPC 1997: 75-90
	1996
6		Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu: Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. ISCA 1996: 203-212
	1994
5		Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer: SCISM: A scalable compound instruction set machine. IBM Journal of Research and Development 38(1): 59-78 (1994)
	1993
4		Richard J. Eickemeyer, Stamatis Vassiliadis: A load-instruction unit for pipelined processors. IBM Journal of Research and Development 37(4): 547-564 (1993)
	1992
3		Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis: Interlock collapsing ALU for increased instruction-level parallelism. MICRO 1992: 149-157
	1988
2		Richard J. Eickemeyer, Janak H. Patel: Performance Evaluation of On-Chip Register and Cache Organizations. ISCA 1988: 64-72
	1987
1		Richard J. Eickemeyer, Janak H. Patel: Performance Evaluation of Multiple Register Sets. ISCA 1987: 264-271

Coauthor Index

1	Emrah Acar	[13]
2	Bart Blaner	[5]
3	John M. Borkenhagen	[8]
4	Pradip Bose	[12] [13]
5	Alper Buyuktosunoglu	[12] [13]
6	Lee Eisen	[12]
7	John Griswell	[12]
8	Zhigang Hu	[12]
9	Hans M. Jacobson	[12] [13]
10	Ross E. Johnson	[6] [7]
11	Jody B. Joyner	[11]
12	Ronald N. Kalla	[8] [11]
13	Steven R. Kunkel	[6] [7] [8] [9] [10]
14	Beng-Hong Lim	[7]
15	Mikko H. Lipasti	[9]
16	Shiafun Liu	[6]
17	Doug Logan	[12]
18	Nadeem Malik	[3]
19	Harry M. Mathis	[10]
20	John D. McCalpin	[10]
21	Alex E. Mericas	[10]
22	Timothy J. Mullins	[9]
23	Brian O'Krafka	[9]
24	Janak H. Patel	[1] [2]
25	Harold Rosenberg	[9]
26	Balaram Sinharoy	[11] [12]
27	Mark S. Squillante	[6] [7]
28	Joel M. Tendler	[11] [12]
29	Steven P. Vanderwiel	[9]
30	Stamatis Vassiliadis	[3] [4] [5]
31	Philip L. Vitale	[9]
32	Larry D. Whitley	[9]
33	Ching-Farn Eric Wu	[7]
34	Victor V. Zyuban	[12]

Colors in the list of coauthors

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