Stephan Eggersglüß

	2011
18		Stephan Eggersglüß, Rolf Drechsler: As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE 2011: 1291-1296
17		Stephan Eggersglüß, Rolf Drechsler: Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1411-1415 (2011)
	2010
16		Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler: Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. European Test Symposium 2010: 176-181
15		Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652
14		Daniel Tille, Stephan Eggersglüß, Rolf Drechsler: Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1125-1130 (2010)
13		Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler: MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electronic Testing 26(3): 307-322 (2010)
12		Stephan Eggersglüß: Robust algorithms for high quality test pattern generation using Boolean satisfiability. University of Bremen 2010: 1-182
	2009
11		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille: Test Pattern Generation using Boolean Proof Engines. Springer 2009: I-XII, 1-192
10		Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182
9		Stephan Eggersglüß, Rolf Drechsler: Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. European Test Symposium 2009: 81-86
8		Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler: Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230
7		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille: Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it - Information Technology 51(2): 102-111 (2009)
	2008
6		Stephan Eggersglüß, Rolf Drechsler: On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99
5		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
	2007
4		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674
3		Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
2		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
1		Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93

Coauthor Index

1	Walter Anheier	[8]
2	Jens Bargfrede	[8]
3	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [17] [18]
4	Görschwin Fey	[1] [2] [3] [4] [5] [7] [11] [13]
5	Andreas Glowatz	[2] [3] [5] [13]
6	Daniel Große	[1]
7	Friedrich Hapke	[2] [3] [5] [13]
8	Rene Krenz-Baath	[16]
9	Murthy Palla	[8]
10	Jürgen Schlöffel	[2] [3] [5] [7] [13] [16]
11	Daniel Tille	[3] [5] [7] [10] [11] [14] [15] [16]
12	Robert Wille	[1]

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