 | 2012 |
| 18 |  | Ye Gao,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
An out-of-order vector processing mechanism for multimedia applications.
Conf. Computing Frontiers 2012: 233-236 |
| 17 |  | Masayuki Sato,
Yusuke Tobo,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A capacity-efficient insertion policy for dynamic cache resizing mechanisms.
Conf. Computing Frontiers 2012: 265-268 |
| 2011 |
| 16 |  | Ling Xu,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A Network Clustering Algorithm for Sybil-Attack Resisting.
IEICE Transactions 94-D(12): 2345-2352 (2011) |
| 15 |  | Isao Kotera,
Kenta Abe,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
Power-Aware Dynamic Cache Partitioning for CMPs.
T. HiPEAC 3: 135-153 (2011) |
| 2010 |
| 14 |  | Yusuke Funaya,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
Cache partitioning strategies for 3-D stacked vector processors.
3DIC 2010: 1-6 |
| 13 |  | Ryusuke Egawa,
Yusuke Funaya,
Ryu-ichi Nagaoka,
Akihiro Musa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
Design and early evaluation of a 3-D die stacked chip multi-vector processor.
3DIC 2010: 1-8 |
| 12 |  | Ye Gao,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications.
DSD 2010: 412-415 |
| 11 |  | Masayuki Sato,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A Majority-Based Control Scheme for Way-Adaptable Caches.
Facing the Multicore-Challenge 2010: 16-28 |
| 10 |  | Masayuki Sato,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A voting-based working set assessment scheme for dynamic cache resizing mechanisms.
ICCD 2010: 98-105 |
| 9 |  | Yoshitomo Murata,
Ryusuke Egawa,
Manabu Higashida,
Hiroaki Kobayashi:
A History-Based Job Scheduling Mechanism for the Vector Computing Cloud.
SAINT 2010: 125-128 |
| 8 |  | Ken-ichi Suzuki,
Yoshiyuki Kaeriyama,
Kazuhiko Komatsu,
Ryusuke Egawa,
Nobuyuki Ohba,
Hiroaki Kobayashi:
A Fast Ray-Tracing Using Bounding Spheres and Frustum Rays for Dynamic Scene Rendering.
IEICE Transactions 93-D(4): 891-902 (2010) |
| 2009 |
| 7 |  | Yusuke Funaya,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
3D on-chip memory for the vector architecture.
3DIC 2009: 1-6 |
| 6 |  | Ryusuke Egawa,
Jubee Taday,
Hiroaki Kobayashi,
Gensuke Gotoy:
Evaluation of fine grain 3-D integrated arithmetic units.
3DIC 2009: 1-8 |
| 5 |  | Takashi Soga,
Akihiro Musa,
Youichi Shimomura,
Ryusuke Egawa,
Ken'ichi Itakura,
Hiroyuki Takizawa,
Koki Okabe,
Hiroaki Kobayashi:
Performance evaluation of NEC SX-9 using real science and engineering applications.
SC 2009 |
| 2008 |
| 4 |  | Chainan Satayapiwat,
Ryusuke Egawa,
Hiroyuki Takizawa,
Hiroaki Kobayashi:
A Utility-Based Double Auction Mechanism for Efficient Grid Resource Allocation.
ISPA 2008: 252-260 |
| 3 |  | Akihoro Musa,
Yoshiei Sato,
Takashi Soga,
Ryusuke Egawa,
Hiroyuki Takizawa,
Koki Okabe,
Hiroaki Kobayashi:
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.
ISPA 2008: 335-342 |
| 2004 |
| 2 |  | Kentaro Sano,
Chiaki Takagi,
Ryusuke Egawa,
Ken-ichi Suzuki,
Tadao Nakamura:
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm.
ITCC (1) 2004: 572-578 |
| 2001 |
| 1 |  | Masa-Aki Fukase,
Ryusuke Egawa,
Tomoaki Sato,
Tadao Nakamura:
Scaling Up Of Wave Pipelines.
VLSI Design 2001: 439-445 |