T. Egan

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2005

1 T. Egan, S. Mourad: Design-for-testability for embedded delay-locked loops. IEEE Trans. VLSI Syst. 13(8): 984-988 (2005)

	2005
1		T. Egan, S. Mourad: Design-for-testability for embedded delay-locked loops. IEEE Trans. VLSI Syst. 13(8): 984-988 (2005)

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