Costas Efstathiou

	2011
28		Ioannis Voyiatzis, Costas Efstathiou, H. Antonopoulou: A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. European Test Symposium 2011: 206
	2010
27		Costas Efstathiou: Efficient modulo 2N+1 subtractors for weighted operands. ICECS 2010: 1-4
26		Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou: Fast modulo 2n+1 multi-operand adders and residue generators. Integration 43(1): 42-48 (2010)
25		Ioannis Voyiatzis, Costas Efstathiou: An efficient architecture for accumulator-based test generation of SIC pairs. Microelectronics Journal 41(8): 487-493 (2010)
	2009
24		Haridimos T. Vergos, Costas Efstathiou: Efficient modulo 2n+1 adder architectures. Integration 42(2): 149-157 (2009)
	2008
23		Haridimos T. Vergos, Costas Efstathiou: A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition. IEEE Trans. on Circuits and Systems 55-II(10): 1041-1045 (2008)
	2007
22		Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou: Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. VLSI Syst. 15(4): 461-465 (2007)
21		Haridimos T. Vergos, Costas Efstathiou: Design of efficient modulo 2n+1 multipliers. IET Computers & Digital Techniques 1(1): 49-57 (2007)
	2006
20		Haridimos T. Vergos, Costas Efstathiou: Novel Modulo 2n + 1 Multipliers. DSD 2006: 168-175
	2005
19		Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos: Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005)
18		Haridimos T. Vergos, Costas Efstathiou: On the Design of Efficient Modular Adders. Journal of Circuits, Systems, and Computers 14(5): 965-972 (2005)
	2004
17		Haridimos T. Vergos, Costas Efstathiou: Diminished-1 Modulo 2n + 1 Squarer Design. DSD 2004: 380-386
16		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004)
15		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004)
	2003
14		Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336
13		D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou: An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93
12		Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. ISCAS (5) 2003: 225-228
11		D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou: Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576
10		K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou: A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks. MMNS 2003: 259-271
9		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003)
8		Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou: Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003)
	2002
7		Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos: Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002)
	2001
6		Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217
5		Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou: Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110
	2000
4		Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou: On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304
3		Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos: High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000)
	1990
2		Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis: An Efficient TSC 1-out-of-3 Code Checker. IEEE Trans. Computers 39(3): 407-411 (1990)
	1984
1		Costas Efstathiou, Constantine Halatsis: Modular design of totally self-checking checkers for 1-out-of-n codes. Fehlertolerierende Rechensysteme 1984: 164-176

Coauthor Index

1	H. Antonopoulou	[28]
2	Dimitris Bakalis	[26]
3	Maciej Bellos	[8]
4	Giorgos Dimitrakopoulos	[12] [14] [19]
5	Constantin Halatsis (Constantine Halatsis, Constantinos Halatsis)	[1] [2]
6	Themistoklis Haniotakis (Th. Haniotakis)	[4] [5] [22]
7	John Kalamatianos	[3]
8	Lampros Kalampoukas	[3]
9	K. Katzourakis	[10]
10	Kimon P. Kontovasilis	[10]
11	George Kormentzas (Georgios Kormentzas)	[10]
12	D. G. Nikolos	[11] [13]
13	Dimitris Nikolos	[3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [19] [22]
14	Antonis M. Paschalis	[2]
15	Yiorgos Tsiatouhas (Y. Tsiatouhas)	[4] [5] [22]
16	Haridimos T. Vergos	[3] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [24] [26]
17	Ioannis Voyiatzis	[25] [28]

Colors in the list of coauthors

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