Douglas A. Edwards

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2005

3 Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005)

2004

2 Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23

1 Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673

	2005
3		Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005)
	2004
2		Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23
1		Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673

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