Hisakazu Edamatsu

	1998
4		Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi: Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. ASP-DAC 1998: 241-248
	1996
3		Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa: Design Methodologies for consumer-use video signal processing LSIs. DAC 1996: 497-502
	1994
2		Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu: Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation. IEEE Trans. Computers 43(1): 43-51 (1994)
	1987
1		Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi: Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic 1987: 80-86

Coauthor Index

1	Katsuya Hasegawa	[3]
2	Katsumi Homma	[4]
3	Satoshi Ikawa	[3]
4	Hideyuki Kabuo	[2]
5	Masaru Kakimoto	[4]
6	Yutaka Koike	[4]
7	Shigeo Kuninobu	[1] [2]
8	Akira Miyoshi	[2]
9	Tamotsu Nishiyama	[1]
10	Kinya Tabuchi	[4]
11	Naofumi Takagi	[1]
12	Takashi Taniguchi	[1] [2]
13	Miki Urano	[2]
14	Hitoshi Yamashita	[2]

Colors in the list of coauthors

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