George Economakos

	2011
37		Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos, Dimitrios Soudris: Design and experimentation with low-power morphable multipliers. ICECS 2011: 752-755
36		Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris: Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow. ReConFig 2011: 428-433
35		Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi: High Performance and Area Efficient Flexible DSP Datapath Synthesis. IEEE Trans. VLSI Syst. 19(3): 429-442 (2011)
	2010
34		George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris: Construction of dual mode components for reconfiguration aware high-level synthesis. DATE 2010: 1357-1360
33		Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris: BIT-width exploration over 3D architectures using high-level synthesis. ICECS 2010: 535-538
32		Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. ISCAS 2010: 2598-2601
31		Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. ISVLSI 2010: 104-109
30		Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos: Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures. ISVLSI 2010: 133-138
29		Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. ISVLSI 2010: 486-487
28		Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi: A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. PATMOS 2010: 73-83
	2009
27		George Economakos, Sotirios Xydis: Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. DSD 2009: 164-171
26		George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu: Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. DSD 2009: 791-798
25		Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. ICECS 2009: 415-418
24		George Economakos, Sotirios Xydis: High-level synthesis with coarse grain reconfigurable components. IPDPS 2009: 1-4
23		Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. Integration 42(4): 486-503 (2009)
22		Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: Extending an embedded RISC microprocessor for efficient translation based Java execution. Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 415-429 (2009)
	2008
21		George Economakos: Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. BIBE 2008: 1-6
20		George Economakos, Sotirios Xydis: A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. DSD 2008: 494-499
19		Christoforos E. Economakos, George Economakos: Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. ETFA 2008: 1002-1009
18		Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: An instruction set extension for java bytecodes translation acceleration. ICSAMOS 2008: 116-123
17		Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: A predecoding technique for ILP exploitation in Java processors. Journal of Systems Architecture - Embedded Systems Design 54(7): 707-728 (2008)
	2007
16		Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS 2007: 342-349
15		George Economakos, Christoforos E. Economakos, Sotirios Xydis: Run-time reconfigurable solutions for adaptive control applications. ICINCO-SPSMC 2007: 208-213
14		Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS 2007: 137-144
	2006
13		George Economakos: High-level synthesis with reconfigurable datapath components. IPDPS 2006
12		George Economakos: Behavioral synthesis with SystemC and PSL assertions for interface specification. ISCAS 2006
11		George Economakos, K. Anagnostopoulos: Bit level architectural exploration technique for the design of low power multipliers. ISCAS 2006
	2002
10		George Economakos, Petros Oikonomakos, Ioannis Poulakis, George K. Papakonstantinou, Stamatis Georgoulis: Handling advanced scheduling heuristics under a hardware compiler generation environment. Knowl.-Based Syst. 15(1-2): 3-11 (2002)
	2001
9		George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou: Behavioral synthesis with systemC. DATE 2001: 21-25
8		George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos: A Multi-Lingual Synthesis and Verification Environment. DSD 2001: 8-15
	1999
7		George Economakos, George K. Papakonstantinou: Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. CHARME 1999: 330-333
6		George Economakos, George K. Papakonstantinou: Language Based Design Verification with Semantic Analysis. EUROMICRO 1999: 1268-
	1998
5		George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. DATE 1998: 933-934
4		George Economakos, George K. Papakonstantinou: Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. EUROMICRO 1998: 10091-10098
3		George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. SAC 1998: 45-49
	1997
2		George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas: Hardware compilation using attribute grammars. CHARME 1997: 273-290
1		Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. HPCN Europe 1997: 888-897

Coauthor Index

1	Angelos Amditis	[26]
2	Iraklis Anagnostopoulos	[30]
3	K. Anagnostopoulos	[11]
4	Theodore Andronikos	[1]
5	Alexandros Bartzas	[30]
6	Dimitris Bekiaris	[25] [28] [36]
7	Dionysios Diamantopoulos	[37]
8	Christoforos E. Economakos	[15] [19]
9	Iasonas Filippopoulos	[30]
10	Stamatis Georgoulis	[10]
11	George Kiokes	[26]
12	Ioannis Koutras	[33] [34]
13	Nectarios Koziris	[1]
14	Petros Oikonomakos	[9] [10]
15	Ioannis Panagopoulos	[9]
16	George K. Papakonstantinou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
17	Christos Papameletis	[28]
18	Antonis Papanikolaou	[28] [33]
19	Kiamal Z. Pekmestzi	[2] [14] [16] [17] [18] [22] [23] [25] [28] [29] [31] [32] [35]
20	Ioannis Poulakis	[9] [10]
21	Isidoros Sideris	[17] [18] [22]
22	Christos Skouroumounis	[31] [32]
23	Efstathios Sotiriou-Xanthopoulos	[36] [37]
24	Dimitrios Soudris (D. J. Soudris)	[28] [29] [30] [31] [32] [33] [34] [35] [36] [37]
25	Stergios Stergiou	[8]
26	Panayotis Tsanakas	[1] [2] [3] [5]
27	Nikolaos K. Uzunoglu	[26]
28	Sotirios Xydis	[14] [15] [16] [20] [23] [24] [25] [27] [29] [31] [32] [34] [35]
29	Vassilios Zoukos	[8]

Colors in the list of coauthors

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