![]() | ![]() |
| 2011 | ||
|---|---|---|
| 38 | Alexander W. Rath, Volkan Esen, Wolfgang Ecker: Analog transaction level modeling. HLDVT 2011: 82 | |
| 2010 | ||
| 37 | Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten: TLM+ modeling of embedded HW/SW systems. DATE 2010: 75-80 | |
| 36 | Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jurgen Mossinger, Andreas von Schwerin: Panel Session - Who Is Closing the embedded software design gap? DATE 2010: 932 | |
| 35 | Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten: Model reduction techniques for the formal verification of hardware dependent software. HLDVT 2010: 148-153 | |
| 34 | Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker: Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. HLDVT 2010: 97-102 | |
| 2009 | ||
| 33 | Wolfgang Ecker, Stefan Heinen, Michael Velten: Using a dataflow abstracted virtual prototype for HdS-design. ASP-DAC 2009: 293-300 | |
| 2008 | ||
| 32 | Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin: Industrial IP Integration Flows based on IP-XACT Standards. DATE 2008: 32-37 | |
| 2007 | ||
| 31 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE 2007: 767-772 | |
| 30 | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE 2007: 894-899 | |
| 29 | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten: Requirements and Concepts for Transaction Level Assertion Refinement. IESS 2007: 1-14 | |
| 2006 | ||
| 28 | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten: Case Study on Transaction Level Modeling. FDL 2006: 209-215 | |
| 27 | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit: IP Library For Temporal SystemC Assertions. FDL 2006: 301-309 | |
| 26 | Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten: Requirements and Concepts for Transaction Level Assertions. ICCD 2006 | |
| 25 | Wolfgang Ecker, Volkan Esen, Michael Hull: Execution semantics and formalisms for multi-abstraction TLM assertions. MEMOCODE 2006: 93-102 | |
| 2005 | ||
| 24 | Wolfgang Ecker, Lothar Schrader: Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. GI Jahrestagung (1) 2005: 313 | |
| 2004 | ||
| 23 | P. Jensen, Wolfgang Ecker, T. Kruse, Martin Zambaldi: SystemVerilog: Interface Based Design. FDL 2004: 505-518 | |
| 22 | Martin Zambaldi, Wolfgang Ecker: Extending the RASSP model for Verification. FDL 2004: 536-544 | |
| 21 | Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. Müller: The Formal Simulation Semantics of SystemVerilog. FDL 2004: 568-578 | |
| 20 | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi: Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC 2004: 129-135 | |
| 19 | Martin Zambaldi, Wolfgang Ecker: How to Bridge the Gap Between Simulationand Test. ITC 2004: 1091-1099 | |
| 18 | Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer: A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. IEEE Design & Test of Computers 21(6): 464-471 (2004) | |
| 2003 | ||
| 17 | Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker: Re-use-centric architecture for a fully accelerated testbench environment. DAC 2003: 372-375 | |
| 16 | Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi: Platform-Based Testbench Generation. DATE 2003: 11038-11045 | |
| 15 | Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer: An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. IPDPS 2003: 187 | |
| 2002 | ||
| 14 | Matthias Bauer, Wolfgang Ecker, Renate Henftling, Martin Zambaldi, Andreas Zinn: Verifikation und Wiederverwendung (Verification and Re-Use). it+ti - Informationstechnik und Technische Informatik 44(2): 108-114 (2002) | |
| 2000 | ||
| 13 | Thomas Schneider, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker: An Open VHDL-AMS Simulation Framework. BMAS 2000: 89-94 | |
| 12 | André Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker: Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). it+ti - Informationstechnik und Technische Informatik 42(5): 43- (2000) | |
| 1999 | ||
| 11 | Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn: A Method for Accelerating Test Environments. EUROMICRO 1999: 1477-1480 | |
| 1997 | ||
| 10 | Matthias Bauer, Wolfgang Ecker: Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. DAC 1997: 774-779 | |
| 9 | Michael Mrva, Mike Heuchling, Wolfgang Ecker: The Shall-Prototype-Test Development model. ECBS 1997: 385-391 | |
| 1996 | ||
| 8 | Manfred Selz, Wolfgang Ecker, Eugenio Villar: VHDL synthesis description portability: The need for Level synthesis subsets. Journal of Systems Architecture 42(2): 105-116 (1996) | |
| 7 | Wolfgang Ecker: Verification methods for VHDL RTL-subroutines. Journal of Systems Architecture 42(2): 117-128 (1996) | |
| 1995 | ||
| 6 | Wolfgang Ecker: Semi-dynamic scheduling of synchronization-mechanisms. EURO-DAC 1995: 374-379 | |
| 5 | Wolfgang Ecker, Manfred Huber: VHDL-based communication and synchronization synthesis. EURO-DAC 1995: 458-462 | |
| 4 | Wolfgang Ecker: A classification of design steps and their verification. EURO-DAC 1995: 536-541 | |
| 1994 | ||
| 3 | Wolfgang Ecker, Manfred Glesner, Andreas Vombach: Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC 1994: 624-629 | |
| 1993 | ||
| 2 | Wolfgang Ecker, Sabine März: System-Level Specification and Design Using VHDL: A Case Study. CHDL 1993: 505-522 | |
| 1 | Wolfgang Ecker, M. Hofmeister: State look ahead technique for cycle optimization of interacting finite state Moore machines. ICCAD 1993: 392-397 | |
Colors in the list of coauthors
Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page