 | 2011 |
| 8 |  | Yung-Chih Chen,
Soumya Eachempati,
Chun-Yao Wang,
Suman Datta,
Yuan Xie,
Vijaykrishnan Narayanan:
Automated mapping for reconfigurable single-electron transistor arrays.
DAC 2011: 878-883 |
| 7 |  | Asit K. Mishra,
Aditya Yanamandra,
Reetuparna Das,
Soumya Eachempati,
Ravi R. Iyer,
Narayanan Vijaykrishnan,
Chita R. Das:
RAFT: A router architecture with frequency tuning for on-chip networks.
J. Parallel Distrib. Comput. 71(5): 625-640 (2011) |
| 2010 |
| 6 |  | Aditya Yanamandra,
Soumya Eachempati,
Niranjan Soundararajan,
Vijaykrishnan Narayanan,
Mary Jane Irwin,
Ramakrishnan Krishnan:
Optimizing power and performance for reliable on-chip networks.
ASP-DAC 2010: 431-436 |
| 2009 |
| 5 |  | Reetuparna Das,
Soumya Eachempati,
Asit K. Mishra,
Narayanan Vijaykrishnan,
Chita R. Das:
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.
HPCA 2009: 175-186 |
| 4 |  | Asit K. Mishra,
Reetuparna Das,
Soumya Eachempati,
Ravishankar R. Iyer,
Narayanan Vijaykrishnan,
Chita R. Das:
A case for dynamic frequency tuning in on-chip networks.
MICRO 2009: 292-303 |
| 2008 |
| 3 |  | Dongkook Park,
Soumya Eachempati,
Reetuparna Das,
Asit K. Mishra,
Yuan Xie,
Narayanan Vijaykrishnan,
Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
ISCA 2008: 251-261 |
| 2007 |
| 2 |  | Soumya Eachempati,
Arthur Nieuwoudt,
Aman Gayasen,
Narayanan Vijaykrishnan,
Yehia Massoud:
Assessing carbon nanotube bundle interconnect for future FPGA architectures.
DATE 2007: 307-312 |
| 1 |  | Soumya Eachempati,
Narayanan Vijaykrishnan,
Arthur Nieuwoudt,
Yehia Massoud:
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.
ISVLSI 2007: 516-517 |