Avijit Dutta

	2011
11		Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab: A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC 2011: 1-9
10		Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9
	2008
9		Avijit Dutta, Abhijit Jas: Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. ISQED 2008: 68-73
	2007
8		Avijit Dutta, Nur A. Touba: Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT 2007: 3-11
7		Avijit Dutta, Nur A. Touba: Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. VTS 2007: 349-354
	2006
6		Avijit Dutta, Nur A. Touba: Synthesis of Efficient Linear Test Pattern Generators. DFT 2006: 206-214
5		Avijit Dutta, David Z. Pan: Partial Functional Manipulation Based Wirelength Minimization. ICCD 2006
4		Avijit Dutta, Nur A. Touba: Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. ITC 2006: 1-9
3		Avijit Dutta, Nur A. Touba: Iterative OPDD Based Signal Probability Calculation. VTS 2006: 72-77
	2005
2		Avijit Dutta, Terence Rodrigues, Nur A. Touba: Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. ISVLSI 2005: 200-205
1		Avijit Dutta, Nur A. Touba: Synthesis of nonintrusive concurrent error detection using an even error detecting function. ITC 2005: 8

Coauthor Index

1	Brady Benware	[11]
2	Wu-Tung Cheng	[11]
3	Jakub Janicki	[10]
4	Abhijit Jas	[9]
5	Mark Kassab	[10] [11]
6	Grzegorz Mrugalski	[10]
7	Nilanjan Mukherjee	[10]
8	David Z. Pan (David Zhigang Pan)	[5]
9	Janusz Rajski	[10]
10	Terence Rodrigues	[2]
11	Manish Sharma	[11]
12	Nur A. Touba	[1] [2] [3] [4] [6] [7] [8]
13	Jerzy Tyszer	[10]

Colors in the list of coauthors

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