Yaseer A. Durrani

	2011
6		Yaseer A. Durrani: Efficient power macromodeling technique for conventional MOS transistors. ICEEI 2011: 1-7
	2009
5		Yaseer A. Durrani, Teresa Riesgo: Power estimation technique for DSP architectures. Digital Signal Processing 19(2): 213-219 (2009)
	2007
4		Yaseer A. Durrani, Ana Abril, Teresa Riesgo: Efficient Power Macromodeling Technique for IP-Based Digital System. ISCAS 2007: 1145-1148
3		Yaseer A. Durrani, Teresa Riesgo: Architectural Power Analysis for Intellectual Property-Based Digital System. J. Low Power Electronics 3(3): 271-279 (2007)
	2006
2		Yaseer A. Durrani, Teresa Riesgo, Felipe Machado: Power estimation for register transfer level by genetic algorithm. ICINCO-RA 2006: 527-530
1		Yaseer A. Durrani, Teresa Riesgo: Power Macromodeling for High Level Power Estimation. ReCoSoC 2006: 232-236

Coauthor Index

1	Ana Abril	[4]
2	Felipe Machado	[2]
3	Teresa Riesgo	[1] [2] [3] [4] [5]

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