Doron Drusinsky

	2011
27		James Bret Michael, Doron Drusinsky, Thomas W. Otani, Man-tak Shing: Verification and Validation for Trustworthy Software Systems. IEEE Software 28(6): 86-92 (2011)
	2010
26		Kevin D. Foster, John J. Shea, Doron Drusinsky, James Bret Michael, Thomas W. Otani, Man-tak Shing: Removing the Boundaries: Steps Toward a Cloud Nirvana. GrC 2010: 167-171
25		Doron Drusinsky, Man-tak Shing: Validating quality attribute requirements via execution-based model checking. International Symposium on Rapid System Prototyping 2010: 1-7
	2009
24		Doron Drusinsky, Man-tak Shing: Using UML Statecharts with Knowledge Logic Guards. MoDELS 2009: 586-590
	2008
23		Doron Drusinsky, James Bret Michael, Thomas W. Otani, Man-tak Shing: Validating UML Statechart-Based Assertions Libraries for Improved Reliability and Assurance. SSIRI 2008: 47-51
22		Doron Drusinsky, James Bret Michael, Man-tak Shing: A framework for computer-aided validation. ISSE 4(2): 161-168 (2008)
	2007
21		Doron Drusinsky, Man-tak Shing: Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation. IEEE International Workshop on Rapid System Prototyping 2007: 82-88
20		Thomas W. Otani, Mikhail Auguston, Thomas S. Cook, Doron Drusinsky, James Bret Michael, Man-tak Shing: A design pattern for using non-developmental items in real-time Java. JTRES 2007: 135-143
19		Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir: Creating and Validating Embedded Assertion Statecharts. IEEE Distributed Systems Online 8(5): (2007)
	2006
18		Doron Drusinsky: Modeling and verification using UML statecharts - a working guide to reactive system design, runtime monitoring and execution-based model checking. Elsevier 2006: I-XII, 1-306
17		Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir: Creation and Validation of Embedded Assertion Statecharts. IEEE International Workshop on Rapid System Prototyping 2006: 17-23
16		Doron Drusinsky: On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata. J. UCS 12(5): 482-498 (2006)
	2005
15		Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir: Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP. IEEE International Workshop on Rapid System Prototyping 2005: 105-110
14		Man-tak Shing, Doron Drusinsky: Architectural Design, Behavior Modeling and Run-Time Verification of Network Embedded Systems. Monterey Workshop 2005: 281-303
13		Doron Drusinsky: Semantics and Runtime Monitoring of TLCharts: Statechart Automata with Temporal Logic Conditioned Transitions. Electr. Notes Theor. Comput. Sci. 113: 3-21 (2005)
	2004
12		Doron Drusinsky, Man-tak Shing: TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions. IEEE International Workshop on Rapid System Prototyping 2004: 29-36
11		Doron Drusinsky: Automatic Simulation of Network Problems in UDP-Based Java Programs Temporal Logic and Natural Language Conditioned Transitions. IPDPS 2004
10		Guillaume P. Brat, Doron Drusinsky, Dimitra Giannakopoulou, Allen Goldberg, Klaus Havelund, Michael R. Lowry, Corina S. Pasareanu, Arnaud Venet, Willem Visser, Richard Washington: Experimental Evaluation of Verification and Validation Tools on Martian Rover Software. Formal Methods in System Design 25(2-3): 167-198 (2004)
	2003
9		Cyrille Artho, Doron Drusinsky, Allen Goldberg, Klaus Havelund, Michael R. Lowry, Corina S. Pasareanu, Grigore Rosu, Willem Visser: Experiments with Test Case Generation and Runtime Analysis. Abstract State Machines 2003: 87-107
8		Doron Drusinsky: Monitoring Temporal Rules Combined with Time Series. CAV 2003: 114-117
7		Doron Drusinsky, Man-tak Shing: Verification of Timing Properties in Rapid System Prototyping. IEEE International Workshop on Rapid System Prototyping 2003: 47-
6		Doron Drusinsky, Garth Watney: Applying Run-Time Monitoring to the Deep-Impact Fault Protection Engine. SEW 2003: 127
5		Doron Drusinsky, Man-tak Shing: Monitoring Temporal Logic Specifications Combined with Time Series Constraints. J. UCS 9(11): 1261-1276 (2003)
	2000
4		Doron Drusinsky: The Temporal Rover and the ATG Rover. SPIN 2000: 323-330
	1994
3		Doron Drusinsky, David Harel: On the Power of Bounded Concurrency I: Finite Automata. J. ACM 41(3): 517-539 (1994)
	1989
2		Doron Drusinsky, David Harel: Using statecharts for hardware description and synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 798-807 (1989)
	1988
1		Doron Drusinsky, David Harel: On the Power of Cooperative Concurrency. Concurrency 1988: 74-103

Coauthor Index

1	Cyrille Artho (Cyrille Valentin Artho)	[9]
2	Mikhail Auguston	[20]
3	Guillaume P. Brat	[10]
4	Thomas S. Cook	[20]
5	Kadir Alpaslan Demir	[15] [17] [19]
6	Kevin D. Foster	[26]
7	Dimitra Giannakopoulou	[10]
8	Allen Goldberg	[9] [10]
9	David Harel	[1] [2] [3]
10	Klaus Havelund	[9] [10]
11	Michael R. Lowry	[9] [10]
12	James Bret Michael (J. Bret Michael, Bret Michael)	[20] [22] [23] [26] [27]
13	Thomas W. Otani	[20] [23] [26] [27]
14	Corina S. Pasareanu	[9] [10]
15	Grigore Rosu	[9]
16	John J. Shea	[26]
17	Man-tak Shing	[5] [7] [12] [14] [15] [17] [19] [20] [21] [22] [23] [24] [25] [26] [27]
18	Arnaud Venet	[10]
19	Willem Visser	[9] [10]
20	Richard Washington	[10]
21	Garth Watney	[6]

Colors in the list of coauthors

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