Yong Dou

	2012
53		Guiming Wu, Yong Dou, Junqing Sun, Gregory D. Peterson: A High Performance and Memory Efficient LU Decomposer on FPGAs. IEEE Trans. Computers 61(3): 366-378 (2012)
52		Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo: Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA. IEICE Transactions 95-B(5): 1602-1611 (2012)
	2011
51		Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou: FPGA Implementation of Variable-Precision Floating-Point Arithmetic. APPT 2011: 127-141
50		Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang: VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. FPL 2011: 252-257
49		Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo: Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. ICCD 2011: 219-225
48		Yuanwu Lei, Yong Dou, Jie Zhou: FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. IEICE Transactions 94-D(11): 2173-2183 (2011)
	2010
47		Guiming Wu, Yong Dou, Gregory D. Peterson: Blocking LU Decomposition for FPGAs. FCCM 2010: 109-112
46		Guiming Wu, Yong Dou, Miao Wang: High performance and memory efficient implementation of matrix multiplication on FPGAs. FPT 2010: 134-137
45		Guiming Wu, Yong Dou, Miao Wang: Automatic synthesis of processor arrays with local memories on FPGAs. FPT 2010: 249-252
44		Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen: FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS 2010: 325-336
43		Fei Xia, Yong Dou, Guo-Qing Lei: Fpqrna: Hardware-Accelerated Qrna Package for noncoding RNA Gene Detecting on FPGA. J. Bioinformatics and Computational Biology 8(4): 743-761 (2010)
42		Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni: A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25(4): 874-885 (2010)
41		Fei Xia, Yong Dou, Dan Zhou, Xin Li: Fine-grained parallel RNA secondary structure prediction using SCFGs on FPGA. Parallel Computing 36(9): 516-530 (2010)
	2009
40		Yong Dou, Ralf Gruber, Josef M. Joller: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings Springer 2009
39		Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang: A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. APPT 2009: 110-122
38		Jinbo Xu, Yong Dou, YuXing Tang, Xiaodong Wang: Implementation of Rotation Invariant Multi-View Face Detection on FPGA. APPT 2009: 82-94
37		Yong Dou, Fei Xia, Jingfei Jiang: Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. CASES 2009: 107-116
36		Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang: A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. FCCM 2009: 183-190
35		Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu: FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. FPL 2009: 410-416
34		Guiming Wu, Miao Wang, Yong Dou, Fei Xia: Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms. ICPP Workshops 2009: 402-408
33		Guangming Liu, Fei Xia, Yong Dou, Xin Liu: FPGA-based Memory-efficient Parallel RNA Secondary Structure Prediction Accelerator Using SCFGs. PDPTA 2009: 814-820
32		Fei Xia, Yong Dou, Xingming Zhou, Xuejun Yang, Jiaqing Xu, Yang Zhang: Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA. BMC Bioinformatics 10(S-1): (2009)
31		Jinbo Xu, Yong Dou, Zhengbin Pang: A Reconfigurable Architecture for Rotation Invariant Multi-View Face Detection Based on a Novel Two-Stage Boosting Method. EURASIP J. Adv. Sig. Proc. 2009: (2009)
30		Bao-Feng Li, Yong Dou, Haifang Zhou, Xingming Zhou: FPGA Accelerator for Wavelet-Based Automated Global Image Registration. EURASIP J. Emb. Sys. 2009: (2009)
29		Dawei Wang, Sikun Li, Yong Dou: Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications. JSW 4(1): 81-89 (2009)
28		Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou: A coarse-grained reconfigurable computing architecture with loop self-pipelining. Science in China Series F: Information Sciences 52(4): 575-587 (2009)
	2008
27		Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong: Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ARC 2008: 254-259
26		Fei Xia, Yong Dou, Jinbo Xu: Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension. ARC 2008: 39-50
25		Dawei Wang, Sikun Li, Yong Dou: Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. ASP-DAC 2008: 679-684
24		Fei Xia, Yong Dou, Jiaqing Xu: Fine-Grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA. BIOCOMP 2008: 538-544
23		Fei Xia, Yong Dou, Jiaqing Xu: Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension. BIRD 2008: 43-57
22		Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong: Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. HPCC 2008: 182-189
21		Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang: Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. ICCD 2008: 240-247
20		Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei: Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA. ICESS 2008: 616-620
19		Bao-Feng Li, Yong Dou: Subblock-Based BPE Scheme to Conquer Mismatch in Memory Access Pattern. IIH-MSP 2008: 814-817
18		Yong Dou, Lin Deng, Jinhui Xu, Yi Zheng: DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor. ISPA 2008: 170-179
17		Jinbo Xu, Yong Dou, Jie Zhou: Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme. NAS 2008: 334-341
	2007
16		Fei Xia, Yong Dou: Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA. APPT 2007: 90-99
15		Yazhuo Dong, Yong Dou, Jie Zhou: Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. ARC 2007: 110-121
14		Yong Dou, Jinhui Xu, Guiming Wu: The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC 2007: 155-166
13		Xiaodong Yang, Shengmei Mou, Yong Dou: FPGA-Accelerated Molecular Dynamics Simulations: An Overview. ARC 2007: 293-301
12		Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou: FPGA SAR Processor with Window Memory Accesses. ASAP 2007: 95-100
11		Yazhuo Dong, Yong Dou: A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. ASP-DAC 2007: 523-528
10		Yong Dou, Jinbo Xu: FPGA-Accelerated Active Shape Model for Real-Time People Tracking. Asia-Pacific Computer Systems Architecture Conference 2007: 268-279
9		Sikun Li, Dawei Wang, Tun Li, Yong Dou: Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization. CSCWD 2007: 133-138
8		Jinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou: FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications. DSD 2007: 432-435
7		Bao-Feng Li, Yong Dou: FIDP: A Novel Architecture for Lifting-Based 2D DWT in JPEG2000. MMM (2) 2007: 373-382
	2006
6		Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong: Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. Asia-Pacific Computer Systems Architecture Conference 2006: 567-573
5		Song Lu, BaoHua Fan, Yong Dou, Xiaodong Yang: Clustering Multicast on Hypercube Network. HPCC 2006: 61-70
4		Xuejun Yang, Yong Dou, Qingfeng Hu: Progress and Challenges in High Performance Computer Technology. J. Comput. Sci. Technol. 21(5): 674-681 (2006)
	2005
3		YuXing Tang, Kun Deng, Xiaodong Wang, Yong Dou, Xingming Zhou: RIMP: Runtime Implicit Predication. APPT 2005: 71-80
2		Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev: 64-bit floating-point FPGA matrix multiplication. FPGA 2005: 86-95
	2003
1		Yong Dou, Xicheng Lu: LEAP: A Data Driven Loop Engine on Array Processor. APPT 2003: 12-22

Coauthor Index

1	Xiaoyang Chen	[35]
2	Kun Deng	[3]
3	Lin Deng	[18]
4	Yazhuo Dong	[6] [11] [15] [20] [22] [27]
5	Qiang Dou	[8]
6	BaoHua Fan	[5]
7	Georgi Gaydadjiev (Georgi Nedeltchev Gaydadjiev)	[2]
8	Ralf Gruber	[40]
9	Song Guo	[44] [49] [51] [52]
10	Qingfeng Hu	[4]
11	Jingfei Jiang	[36] [37] [42]
12	Josef M. Joller	[40]
13	Georgi Kuzmanov	[2]
14	Guo-Qing Lei	[43]
15	Yuanwu Lei	[12] [20] [22] [27] [35] [36] [39] [42] [44] [48] [49] [50] [51] [52]
16	Bao-Feng Li	[7] [19] [30]
17	Junfeng Li	[8]
18	Rongchun Li	[52]
19	Sikun Li	[9] [25] [29]
20	Tun Li	[9]
21	Xin Li	[41]
22	Guangming Liu	[33]
23	Xin Liu	[33]
24	Song Lu	[5]
25	Xicheng Lu	[1]
26	Shengmei Mou	[13]
27	Shi-Ce Ni	[42] [52]
28	Zhengbin Pang	[31]
29	Gregory D. Peterson	[47] [53]
30	Li Shen	[44] [49]
31	Junqing Sun	[53]
32	YuXing Tang	[3] [38]
33	Yuxing Tang	[39]
34	Stamatis Vassiliadis	[2]
35	Dawei Wang	[9] [25] [29]
36	Miao Wang	[34] [36] [45] [46]
37	Sufeng Wang	[50]
38	Xiaodong Wang	[3] [38]
39	Guiming Wu	[6] [14] [28] [34] [36] [42] [44] [45] [46] [47] [53]
40	Fei Xia	[16] [21] [23] [24] [26] [32] [33] [34] [37] [39] [41] [43]
41	Jiaqing Xu	[23] [24] [32]
42	Jinbo Xu	[8] [10] [17] [22] [26] [31] [35] [38]
43	Jinhui Xu	[6] [14] [18] [28]
44	Xiaodong Yang	[5] [13]
45	Xuejun Yang	[4] [21] [32]
46	Yang Zhang	[32]
47	Jianxun Zhao	[39]
48	Yi Zheng	[18]
49	Dan Zhou	[41]
50	Haifang Zhou	[30]
51	Jie Zhou	[12] [15] [17] [20] [22] [27] [35] [36] [39] [42] [44] [48] [49] [50] [51]
52	Xingming Zhou	[3] [8] [12] [21] [28] [30] [32]

Colors in the list of coauthors

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page