Gary S. Ditlow

	2011
5		Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter Wendel, Leland Chang: A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258
	2007
4		Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan: Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262
	1999
3		Gary S. Ditlow, Anshul Gupta, Richard L. Moore, David Moran, Ralph Williams, Tom Wilkins: Parallel Analysis of IC Power Distribution Networks. PPSC 1999
	1992
2		D. A. Zein, O. P. Engel, Gary S. Ditlow: HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. DAC 1992: 432-437
	1984
1		Jacob Savir, Gary S. Ditlow, Paul H. Bardell: Random Pattern Testability. IEEE Trans. Computers 33(1): 79-90 (1984)

Coauthor Index

1	Paul H. Bardell	[1]
2	Leland Chang	[5]
3	Sherman M. Dance	[5]
4	Sebastian Ehrenreich	[5]
5	O. P. Engel	[2]
6	Bruce M. Fleischer	[5]
7	Thomas W. Fox	[5]
8	Anshul Gupta	[3]
9	Kyle M. Holmes	[5]
10	Stephen V. Kosonocky	[4]
11	Junichi Mihara	[5]
12	Robert K. Montoye	[5]
13	Richard L. Moore	[3]
14	David Moran	[3]
15	Yutaka Nakamura	[5]
16	Shohji Onishi	[5]
17	Zhenyu Qi	[4]
18	Jacob Savir	[1]
19	Robert Shearer	[5]
20	Mircea R. Stan	[4]
21	Salvatore N. Storino	[5]
22	Dieter Wendel	[5]
23	Tom Wilkins	[3]
24	Ralph Williams	[3]
25	D. A. Zein	[2]
26	Matthew M. Ziegler	[4]

Colors in the list of coauthors

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