Florent de Dinechin

	2012
45		Florent de Dinechin, Laurent-Stéphane Didier: Table-Based Division by Small Integer Constants. ARC 2012: 53-63
44		Florent de Dinechin: Multiplication by Rational Constants. IEEE Trans. on Circuits and Systems 59-II(2): 98-102 (2012)
	2011
43		Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco: An FPGA architecture for solving the Table Maker's Dilemma. ASAP 2011: 187-194
42		Florent de Dinechin: The Arithmetic Operators You Will Never See in a Microprocessor. IEEE Symposium on Computer Arithmetic 2011: 189-190
41		Florent de Dinechin, Bogdan Pasca: Designing Custom Arithmetic Data Paths with FloPoCo. IEEE Design & Test of Computers 28(4): 18-27 (2011)
40		Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond: Certifying the Floating-Point Implementation of an Elementary Function Using Gappa. IEEE Trans. Computers 60(2): 242-253 (2011)
	2010
39		Jean-Michel Muller, Nicolas Brisebarre, Florent de Dinechin, Claude-Pierre Jeannerod, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Damien Stehlé, Serge Torres: Handbook of Floating-Point Arithmetic. Birkhäuser 2010: I-XXIII, 1-572
38		Florent de Dinechin, Mioara Joldes, Bogdan Pasca: Automatic generation of polynomial-based hardware architectures for function evaluation. ASAP 2010: 216-222
37		Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca: Pipelined FPGA Adders. FPL 2010: 422-427
36		Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy: Multiplicative Square Root Algorithms for FPGAs. FPL 2010: 574-577
35		Florent de Dinechin, Bogdan Pasca: Floating-point exponential functions for DSP-enabled FPGAs. FPT 2010: 110-117
34		Álvaro Vázquez, Florent de Dinechin: Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. FPT 2010: 126-133
33		Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran: Multipliers for floating-point double precision and beyond on FPGAs. SIGARCH Computer Architecture News 38(4): 73-79 (2010)
	2009
32		Florent de Dinechin, Bogdan Pasca: Large multipliers with fewer DSP blocks. FPL 2009: 250-255
31		Florent de Dinechin, Cristian Klein, Bogdan Pasca: Generating high-performance custom floating-point pipelines. FPL 2009: 59-64
	2008
30		Nicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller: Integer and floating-point constant multipliers for FPGAs. ASAP 2008: 239-244
29		Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, Florent de Dinechin: FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System. BIODEVICES (1) 2008: 151-155
28		Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran: When FPGAs are better at floating-point than microprocessors. FPGA 2008: 260
27		Florent de Dinechin, Milos D. Ercegovac, Jean-Michel Muller, Nathalie Revol: Digital Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008
26		Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond: Certifying floating-point implementations using Gappa CoRR abs/0801.0523: (2008)
25		Florent de Dinechin, Christoph Quirin Lauter: Optimizing polynomials for floating-point implementation CoRR abs/0803.0439: (2008)
24		Jérémie Detrey, Florent de Dinechin: Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques 27(6): 673-698 (2008)
	2007
23		Jérémie Detrey, Florent de Dinechin: Floating-Point Trigonometric Functions for FPGAs. FPL 2007: 29-34
22		Jérémie Detrey, Florent de Dinechin, Xavier Pujol: Return of the hardware floating-point elementary function. IEEE Symposium on Computer Arithmetic 2007: 161-168
21		Florent de Dinechin, Christoph Quirin Lauter, Jean-Michel Muller: Fast and correctly rounded logarithms in double-precision. ITA 41(1): 85-102 (2007)
20		Jérémie Detrey, Florent de Dinechin: Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems 31(8): 537-545 (2007)
19		Jérémie Detrey, Florent de Dinechin: A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. VLSI Signal Processing 49(1): 161-175 (2007)
	2006
18		Sylvain Collange, Jérémie Detrey, Florent de Dinechin: Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. DSD 2006: 197-203
17		Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond: Assisted verification of elementary functions using Gappa. SAC 2006: 1318-1322
	2005
16		Jérémie Detrey, Florent de Dinechin: Table-based polynomials for fast hardware function evaluation. ASAP 2005: 328-333
15		Jérémie Detrey, Florent de Dinechin: A Parameterized Floating-Point Exponential Function for FPGAs. FPT 2005: 27-34
14		Florent de Dinechin, Alexey V. Ershov, Nicolas Gast: Towards the Post-Ultimate libm. IEEE Symposium on Computer Arithmetic 2005: 288-295
13		Florent de Dinechin, Arnaud Tisserand: Multipartite Table Methods. IEEE Trans. Computers 54(3): 319-330 (2005)
12		Jérémie Detrey, Florent de Dinechin: Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et Science Informatiques 24(6): 625-643 (2005)
	2004
11		Jérémie Detrey, Florent de Dinechin: Second Order Function Approximation Using a Single Multiplication on FPGAs. FPL 2004: 221-230
	2003
10		David Defour, Florent de Dinechin: Software Carry-Save: A Case Study for Instruction-Level Parallelism. PaCT 2003: 207-214
	2002
9		Jérémie Detrey, Florent de Dinechin: Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. IPDPS 2002
	2001
8		Florent de Dinechin, Arnaud Tisserand: Some Improvements on Multipartite Table Methods . IEEE Symposium on Computer Arithmetic 2001: 128-135
	2000
7		Florent de Dinechin, Vincent Lefèvre: Constant Multipliers for FPGAs. PDPTA 2000
6		Florent de Dinechin: The Price of Routing in FPGAs. J. UCS 6(2): 227-239 (2000)
	1999
5		Florent de Dinechin, Wayne Luk, Steve McKeever: Towards Adaptable Hierarchical Placement for FPGAs. FPGA 1999: 254
	1997
4		Florent de Dinechin: Libraries of schedule-free operators in Alpha. ASAP 1997: 239-
3		Florent de Dinechin, T. Risset, Sophie Robert: Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. PARCO 1997: 261-268
	1996
2		Florent de Dinechin, Sophie Robert: Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. ASAP 1996: 381-
1		Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov: A Regular VLSI Array for an Irregular Algorithm. IRREGULAR 1996: 195-200

Coauthor Index

1	Rumen Andonov	[1]
2	Sebastian Banescu	[33]
3	Nicolas Brisebarre	[30] [39]
4	Sylvain Collange	[18]
5	Laura Cret	[29]
6	Octavian Cret	[28] [29]
7	David Defour	[10]
8	Jérémie Detrey	[9] [11] [12] [15] [16] [18] [19] [20] [22] [23] [24] [28]
9	Laurent-Stéphane Didier	[45]
10	Milos D. Ercegovac	[27]
11	Alexey V. Ershov	[14]
12	Nicolas Gast	[14]
13	Claude-Pierre Jeannerod	[39]
14	Mioara Joldes	[36] [38]
15	Cristian Klein	[31]
16	Christoph Quirin Lauter	[17] [21] [25] [26] [40]
17	Vincent Lefèvre	[7] [39]
18	Wayne Luk	[5]
19	Steve McKeever	[5]
20	Guillaume Melquiond	[17] [26] [39] [40]
21	Jean-Michel Muller	[21] [27] [30] [39] [43]
22	Hong Diep Nguyen	[37]
23	Bogdan Pasca	[31] [32] [33] [35] [36] [37] [38] [41] [43]
24	Alexandru Plesco	[43]
25	Xavier Pujol	[22]
26	Sanjay V. Rajopadhye	[1]
27	Nathalie Revol	[27] [39]
28	Guillaume Revy	[36]
29	T. Risset	[3]
30	Sophie Robert	[2] [3]
31	Damien Stehlé	[39]
32	Arnaud Tisserand	[8] [13]
33	Serge Torres	[39]
34	Ionut Trestian	[29]
35	Radu Tudoran	[28] [29] [33]
36	Lucia Vacariu	[29]
37	Álvaro Vázquez	[34]
38	Doran Wilde	[1]

Colors in the list of coauthors

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page