Andreas Dielacher

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2010

2 Matthias Függer, Andreas Dielacher, Ulrich Schmid: How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. EDCC 2010: 230-239

2009

1 Andreas Dielacher, Matthias Függer, Ulrich Schmid: Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining. PODC 2009: 276-277

	2010
2		Matthias Függer, Andreas Dielacher, Ulrich Schmid: How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. EDCC 2010: 230-239
	2009
1		Andreas Dielacher, Matthias Függer, Ulrich Schmid: Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining. PODC 2009: 276-277

Coauthor Index

1 Matthias Függer [1] [2]

2 Ulrich Schmid [1] [2]

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —

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