Jia Di

	2011
20		Guoyuan Fu, H. Alan Mantooth, Jia Di: A 12-bit CMOS current steering D/A converter with a fully differential voltage output. ISQED 2011: 398-404
19		Senthilkumar Chinnappa Gounder Periaswamy, Dale R. Thompson, Jia Di: Fingerprinting RFID Tags. IEEE Trans. Dependable Sec. Comput. 8(6): 938-943 (2011)
	2010
18		Scott Smith, David Roclin, Jia Di: Delay-Insensitive Cell Matrix. CDES 2010: 67-73
17		Scott C. Smith, Waleed Al-Assadi, Jia Di: Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. IEEE Trans. Education 53(3): 349-357 (2010)
16		David Coleman, Jia Di: Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime. J. Low Power Electronics 6(2): 320-324 (2010)
	2009
15		Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith: Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC 2009: 1-5
14		Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di: Glitch-free design for multi-threshold CMOS NCL circuits. ACM Great Lakes Symposium on VLSI 2009: 215-220
13		Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di: Delay-Insensitive Ternary Logic. CDES 2009: 3-0
	2008
12		Senthilkumar Chinnappa Gounder Periaswamy, Dale R. Thompson, Jia Di: Ownership Transfer of RFID Tags based on Electronic Fingerprint. Security and Management 2008: 64-67
11		Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith: Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. J. Low Power Electronics 4(3): 337-348 (2008)
	2007
10		Jia Di, Parag K. Lala: Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J. Electronic Testing 23(2-3): 175-192 (2007)
	2006
9		Jia Di, Dilip P. Vasudevan: Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. DELTA 2006: 149-156
8		Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson: Reversible-logic design with online testability. IEEE T. Instrumentation and Measurement 55(2): 406-414 (2006)
7		Jia Di, Jiann S. Yuan, Ronald F. DeMara: Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. Integration 39(2): 90-112 (2006)
6		Jia Di, Jiann S. Yuan: Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. J. Low Power Electronics 2(2): 201-216 (2006)
	2005
5		Jiann S. Yuan, Jia Di: Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. CDES 2005: 218-223
4		Jia Di, Fengwei Yang: D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications. Circuits, Signals, and Systems 2005: 73-78
3		Jia Di, Parag K. Lala, Dilip P. Vasudevan: On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT 2005: 371-379
	2003
2		Jia Di, Jiann S. Yuan: Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. ACM Great Lakes Symposium on VLSI 2003: 64-67
1		Jia Di, Jiann S. Yuan, Ronald F. DeMara: High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. ISVLSI 2003: 260-261

Coauthor Index

1	Waleed Al-Assadi	[17]
2	Andrew Bailey	[11] [14]
3	David Coleman	[16]
4	Ronald F. DeMara	[1] [7]
5	Guoyuan Fu	[11] [14] [20]
6	Brent Hollosi	[15]
7	Parag K. Lala	[3] [8] [10]
8	H. Alan Mantooth	[20]
9	Ravi Sankar Parameswaran Nair	[13] [15]
10	James Patrick Parkerson	[8]
11	Senthilkumar Chinnappa Gounder Periaswamy	[12] [19]
12	David Roclin	[18]
13	Scott Smith	[18]
14	Scott C. Smith	[11] [13] [15] [17]
15	Dale R. Thompson	[12] [19]
16	Dilip P. Vasudevan	[3] [8] [9]
17	Yuan Xie	[15]
18	Fengwei Yang	[4]
19	Jiann S. Yuan	[1] [2] [5] [6] [7]
20	Ahmad Al Zahrani	[11] [14]
21	Tao Zhang	[15]

Colors in the list of coauthors

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