 | 2010 |
| 20 |  | Narendra Devta-Prasanna,
Arun Gunda,
Sudhakar M. Reddy,
Irith Pomeranz:
Multiple fault activation cycle tests for transistor stuck-open faults.
ITC 2010: 821 |
| 19 |  | Narendra Devta-Prasanna,
Arun Gunda:
Clock Gate Test Points.
ITC 2010: 84-93 |
| 2009 |
| 18 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
Detectability of internal bridging faults in scan chains.
ASP-DAC 2009: 678-683 |
| 17 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
Improving the Detectability of Resistive Open Faults in Scan Cells.
DFT 2009: 383-391 |
| 16 |  | Narendra Devta-Prasanna,
Sandeep Kumar Goel,
Arun Gunda,
Mark Ward,
P. Krishnamurthy:
Accurate measurement of small delay defect coverage of test patterns.
ITC 2009: 1-10 |
| 15 |  | Sandeep Kumar Goel,
Narendra Devta-Prasanna,
Mark Ward:
Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study.
ITC 2009: 1-10 |
| 14 |  | Sandeep Kumar Goel,
Narendra Devta-Prasanna,
Ritesh P. Turakhia:
Effective and Efficient Test Pattern Generation for Small Delay Defect.
VTS 2009: 111-116 |
| 2008 |
| 13 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
DFT 2008: 394-402 |
| 12 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
An Enhanced Logic BIST Architecture for Online Testing.
IOLTS 2008: 10-15 |
| 11 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
Detection of Internal Stuck-open Faults in Scan Chains.
ITC 2008: 1-10 |
| 10 |  | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults An Industrial Case Study.
VTS 2008: 79-84 |
| 9 |  | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Arun Gunda:
Comparative study of centralised and distributed compatibility-based test data compression.
IET Computers & Digital Techniques 2(2): 108-117 (2008) |
| 2007 |
| 8 |  | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Arun Gunda:
Systematic Scan Reconfiguration.
ASP-DAC 2007: 738-743 |
| 7 |  | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Erik Chmelar,
M. Grinchuk,
Arun Gunda:
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 907-918 (2007) |
| 2006 |
| 6 |  | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
Test Generation for Open Defects in CMOS Circuits.
DFT 2006: 41-49 |
| 5 |  | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
European Test Symposium 2006: 185-192 |
| 2005 |
| 4 |  | Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Arun Gunda,
P. Krishnamurthy,
Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Asian Test Symposium 2005: 202-207 |
| 3 |  | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Arun Gunda:
Should Illinois-Scan Based Architectures be Centralized or Distributed?
DFT 2005: 406-414 |
| 2 |  | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
ICCD 2005: 471-474 |
| 1 |  | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
Methods for improving transition delay fault coverage using broadside tests.
ITC 2005: 10 |