Niranjan M. Devashrayee
List of publications from the
 | 2011 |
|---|
| 7 |       | Usha Sandeep Mehta,
Kankar S. Dasgupta,
Niranjan M. Devashrayee:
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey.
VLSI Design 2011: (2011) |
| 6 | | Usha Sandeep Mehta,
Kankar S. Dasgupta,
Nirnjan M. Devashrayee:
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.
VLSI Design 2011: (2011) |
| 2010 |
|---|
| 5 | | Usha Sandeep Mehta,
Niranjan M. Devashrayee,
Kankar S. Dasgupta:
Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead.
ISVLSI 2010: 448-449 |
| 4 | | Usha S. Mehla,
Kankar S. Dasgupta,
Nirnjan M. Devashrayee:
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes.
VLSI Design 2010: 33-38 |
| 3 | | Usha Sandeep Mehta,
Kankar S. Dasgupta,
Nirnjan M. Devashrayee:
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead.
J. Electronic Testing 26(6): 679-688 (2010) |
| 2 | | Usha Sandeep Mehta,
Kankar S. Dasgupta,
Niranjan M. Devashrayee:
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey.
VLSI Design 2010: (2010) |
| 2009 |
|---|
| 1 | | Usha Sandeep Mehta,
Kankar S. Dasgupta,
Nirnjan M. Devashrayee:
Survey of Test Data Compression Technique Emphasizing Code Based Schemes.
DSD 2009: 617-620 |
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