Ed F. Deprettere

	2010
87		Ed F. Deprettere, Todor Stefanov: 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES '10, St. Goar, Germany, June 29-30, 2010 ACM 2010
	2009
86		Ed F. Deprettere, Ana Lucia Varbanescu: Introduction to Mastering Cell BE and GPU Execution Platforms. SAMOS 2009: 275-276
85		Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere: Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. SAMOS 2009: 308-317
	2008
84		Hristo Nikolov, Mark Thompson, Todor Stefanov, Andy D. Pimentel, Simon Polstra, R. Bose, Claudiu Zissulescu, Ed F. Deprettere: Daedalus: toward composable multimedia MP-SoC design. DAC 2008: 574-579
83		Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere: Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. SAMOS 2008: 167-176
82		Bin Jiang, Ed F. Deprettere, Bart Kienhuis: Hierarchical run time deadlock detection in process networks. SiPS 2008: 239-244
81		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM. EURASIP J. Emb. Sys. 2008: (2008)
80		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Systematic and Automated Multiprocessor System Design, Programming, and Implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 542-555 (2008)
79		Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Deriving efficient control in Process Networks with Compaan/Laura. IJES 3(3): 170-180 (2008)
	2007
78		Mark Thompson, Hristo Nikolov, Todor Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere: A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. CODES+ISSS 2007: 9-14
77		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. FPL 2007: 580-584
76		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embedded Comput. Syst. 6(2): (2007)
75		Ed F. Deprettere, Roger Woods, Ingrid Verbauwhede, Erwin A. de Kock: Transforming Signal Processing Applications into Parallel Implementations. EURASIP J. Adv. Sig. Proc. 2007: (2007)
74		Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere: Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007)
	2006
73		Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen: Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. ASAP 2006: 186-190
72		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Multi-processor system design with ESPAM. CODES+ISSS 2006: 211-216
71		Jérôme Lemaitre, Ed F. Deprettere: FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. Euro-Par 2006: 1192-1203
70		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. FPL 2006: 1-6
69		Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: Requirements for Interfacing IP-Components in Re-configurable Platforms. VLSI Signal Processing 43(2-3): 173-184 (2006)
	2005
68		Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Expression Synthesis in Process Networks generated by LAURA. ASAP 2005: 15-21
67		Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: Behavioral specification of control interface for signal processing applications. ASAP 2005: 43-49
66		Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. FCCM 2005: 255-263
65		Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Communication Synthesis in a multiprocessor environment. FPL 2005: 360-365
64		Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos: FPL-3E: Towards Language Support for Reconfigurable Packet Processing. SAMOS 2005: 82-92
63		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Solving Out-of-Order Communication in Kahn Process Networks. VLSI Signal Processing 40(1): 7-18 (2005)
	2004
62		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP 2004: 282-292
61		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Translating affine nested-loop programs to process networks. CASES 2004: 220-229
60		Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE 2004: 340-345
59		Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL 2004: 690-699
58		Sylvain Alliot, Ed F. Deprettere: Architecture Exploration of a Large Scale System. IEEE International Workshop on Rapid System Prototyping 2004: 217-224
57		Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: On the (Re-)Use of IP-Components in Re-configurable Platforms. SAMOS 2004: 264-273
56		Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock: Communication Optimization in Compaan Process Networks. SAMOS 2004: 494-506
55		Laurentiu Nicolae, Ed F. Deprettere: Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. SAMOS 2004: 550-560
54		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES 2004: 62-76
	2003
53		Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere: Context-Aware Process Networks. ASAP 2003: 6-16
52		Todor Stefanov, Ed F. Deprettere: Deriving process networks from weakly dynamic applications in system-level design. CODES+ISSS 2003: 90-96
51		Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere: Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. DATE 2003: 10656-10661
50		Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Laura: Leiden Architecture Research and Exploration Tool. FPL 2003: 911-920
49		Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere: Analysis of joint angle-frequency estimation using ESPRIT. IEEE Transactions on Signal Processing 51(5): 1264-1283 (2003)
48		Bart Kienhuis, Ed F. Deprettere: Modeling Stream-Based Applications Using the SBF Model of Computation. VLSI Signal Processing 34(3): 291-300 (2003)
	2002
47		Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Springer 2002
46		Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP 2002: 17-28
45		Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES 2002: 7-12
44		Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers: A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges 2002: 18-37
43		Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis: Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges 2002: 89-111
42		Ed F. Deprettere, Bart Kienhuis, Richard L. Walke: Preface. Design Autom. for Emb. Sys. 7(4): 303-305 (2002)
41		Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere: Compilation From Matlab to Process Networks Realized in FPGA. Design Autom. for Emb. Sys. 7(4): 385-403 (2002)
	2001
40		Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere: A trace transformation technique for communication refinement. CODES 2001: 134-139
39		Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere: System Level Design with Spade: an M-JPEG Case Study. ICCAD 2001: 31-38
38		Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere: Exploring Embedded-Systems Architectures with Artemis. IEEE Computer 34(11): 57-63 (2001)
37		Jun Ma, Keshab K. Parhi, Ed F. Deprettere: A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms. IEEE Transactions on Signal Processing 49(2): 424-437 (2001)
36		Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere: A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. VLSI Signal Processing 29(3): 197-207 (2001)
	2000
35		Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis: High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP 2000: 79-91
34		Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere: Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES 2000: 13-17
33		Jun Ma, Keshab K. Parhi, Ed F. Deprettere: Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming. IEEE Transactions on Signal Processing 48(8): 2414-2431 (2000)
32		Jun Ma, Keshab K. Parhi, Gerben J. Hekstra, Ed F. Deprettere: Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations. IEEE Transactions on Signal Processing 48(9): 2712-2716 (2000)
31		Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis: Deriving Process Networks from Nested Loop Algorithms. Parallel Processing Letters 10(2/3): 165-176 (2000)
30		Kees-Jan Van der Kolk, Jeong-A. Lee, Ed F. Deprettere: A Floating Point Vectoring Algorithm Based on Fast Rotations. VLSI Signal Processing 25(2): 125-139 (2000)
29		Gerben J. Hekstra, Ed F. Deprettere, Jeong-A. Lee: Guest Editor's Introduction. VLSI Signal Processing 25(2): 99-100 (2000)
	1999
28		Kees-Jan Van der Kolk, Ed F. Deprettere, Jeong-A. Lee: A Floating Point Vectoring Algorithm Based on Fast Rotations. EUROMICRO 1999: 1140-
27		Jun Ma, Keshab K. Parhi, Ed F. Deprettere: Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. ISCAS (3) 1999: 347-350
26		Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock: A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. VLSI Signal Processing 22(1): 9-20 (1999)
	1998
25		Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: The construction of a retargetable simulator for an architecture template. CODES 1998: 125-129
24		W. Bastiaan Kleijn, Huimin Yang, Ed F. Deprettere: Waveform interpolation coding with pitch-spaced subbands. ICSLP 1998
23		Laurens Bierens, Ed F. Deprettere: Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures. VLSI Signal Processing 18(1): 51-64 (1998)
	1997
22		Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP 1997: 338-349
21		Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma: A strategy for determining a Jacobi specific dataflow processor. ASAP 1997: 53-
20		Aweke N. Lemma, W. Bastiaan Kleijn, Ed F. Deprettere: Quantization using wavelet based temporal decomposition of the LSF. EUROSPEECH 1997
19		Gerben J. Hekstra, Ed F. Deprettere: Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation. IEEE Symposium on Computer Arithmetic 1997: 116-125
	1996
18		Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere: Jacobi-Specific Processor Arrays. ASAP 1996: 323-
17		Marc Moonen, Ed F. Deprettere: A fully pipelined RLS-based array for channel equalization. VLSI Signal Processing 14(1): 67-74 (1996)
	1995
16		Li-Sheng Shen, Ed F. Deprettere, Patrick Dewilde: A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading. Computers & Graphics 19(2): 281-296 (1995)
15		H. W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere: Scalable parallel processor array for Jacobi-type matrix computations. Integration 20(1): 41-61 (1995)
	1994
14		Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele: Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS 1994: 129-136
13		Marc Moonen, Filiep J. Vanpoucke, Ed F. Deprettere: Parallel and adaptive high-resolution direction finding. IEEE Transactions on Signal Processing 42(9): 2439-2448 (1994)
	1993
12		Gerben J. Hekstra, Ed F. Deprettere: Floating point Cordic. IEEE Symposium on Computer Arithmetic 1993: 130-137
11		Ed F. Deprettere: Example of combined algorithm development and architecture design. Integration 16(3): 199-220 (1993)
	1992
10		Alle-Jan van der Veen, P. Bas Ober, Ed F. Deprettere: Azimuth and elevation computation in high resolution DOA estimation. IEEE Transactions on Signal Processing 40(7): 1828-1832 (1992)
	1991
9		Li-Sheng Shen, F. A. J. Laarakker, Ed F. Deprettere: Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II). Advances in Computer Graphics Hardware (Machines) 1991: 175-190
8		Alfons A. J. de Lange, Ed F. Deprettere: Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing. IEEE Symposium on Computer Arithmetic 1991: 272-281
7		Alle-Jan van der Veen, Ed F. Deprettere: Parallel VLSI matrix pencil algorithm for high resolution direction finding. IEEE Transactions on Signal Processing 39(2): 383-394 (1991)
6		Ed F. Deprettere: Introduction. VLSI Signal Processing 3(3): 149 (1991)
	1989
5		A. C. Yilmaz, S. Hagestein, Ed F. Deprettere, Patrick Dewilde: A Hardware Algorithm for Fast Realistic Image Synthesis. Advances in Computer Graphics Hardware 1989: 37-60
4		A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick Dewilde: A New Model for the High Level Description and Simulation of VLSI Networks. DAC 1989: 738-741
3		Jichun Bu, Ed F. Deprettere: A VLSI system architecture for high-speed radiative transfer 3D image synthesis. The Visual Computer 5(3): 121-133 (1989)
2		Paul F. C. Krekel, Ed F. Deprettere: A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix. VLSI Signal Processing 1(2): 143-152 (1989)
	1988
1		K. Jainandunsing, Ed F. Deprettere: Design of a Concurrent Computer for Solving Systems of Linear Equations. ISCA 1988: 204-211

Coauthor Index

1	Sylvain Alliot	[57] [58] [67] [69]
2	Shuvra S. Bhattacharyya	[73] [74]
3	Laurens Bierens	[23]
4	Herbert Bos	[64]
5	R. Bose	[84]
6	Jichun Bu	[3]
7	Francky Catthoor	[14]
8	Ioan Cimpian	[56]
9	Mihai-Lucian Cristea	[64]
10	Steven Derrien	[79]
11	Patrick Dewilde	[4] [5] [16]
12	H. W. van Dijk	[15]
13	Hylke W. van Dijk	[18] [53]
14	Cagkan Erbas	[78]
15	S. Hagestein	[5]
16	Tim Harriss	[41]
17	Gerben J. Hekstra	[12] [15] [18] [19] [21] [29] [32]
18	Louis O. Hertzberger (Bob Hertzberger)	[38]
19	A. J. van der Hoeven	[4]
20	Yu Hen Hu	[14]
21	K. Jainandunsing	[1]
22	Bin Jiang	[82]
23	Bart Kienhuis	[22] [25] [26] [31] [34] [35] [41] [42] [43] [44] [45] [46] [48] [50] [54] [59] [60] [61] [62] [63] [65] [68] [74] [76] [79] [82]
24	W. Bastiaan Kleijn	[20] [24]
25	Ming-Yung Ko	[74]
26	Erwin A. de Kock	[26] [51] [56] [75]
27	Kees-Jan Van der Kolk	[28] [30]
28	Paul F. C. Krekel	[2]
29	F. A. J. Laarakker	[9]
30	A. A. de Lange (Alfons A. J. de Lange)	[4] [8]
31	Jeong-A. Lee	[28] [29] [30]
32	Jérôme Lemaitre	[57] [67] [69] [71]
33	Aweke N. Lemma	[20] [49]
34	Paul Lieverse	[26] [35] [36] [38] [39] [40]
35	Jun Ma	[21] [27] [32] [33] [37]
36	Sjoerd Meijer	[85]
37	Heinrich Meyr	[14]
38	Marc Moonen	[13] [17]
39	Dmitry Nadezhkin	[85]
40	Laurentiu Nicolae	[55]
41	Hristo Nikolov	[66] [70] [72] [77] [78] [80] [81] [83] [84]
42	P. Bas Ober	[10]
43	Keshab K. Parhi	[27] [32] [33] [37]
44	Andy D. Pimentel	[38] [78] [83] [84]
45	Simon Polstra	[78] [83] [84]
46	Sebastian Puthenpurayil	[74]
47	Jan M. Rabaey	[14]
48	Edwin Rijpkema	[21] [31] [34] [35] [43]
49	Mainak Sen	[73]
50	Li-Sheng Shen	[9] [16]
51	Henk J. Sips	[53]
52	Todor Stefanov	[39] [45] [50] [52] [60] [66] [70] [72] [73] [77] [78] [80] [81] [83] [84] [85] [87]
53	Jürgen Teich	[47]
54	Lothar Thiele	[14]
55	Mark Thompson	[78] [83] [84]
56	Alexandru Turjan	[46] [54] [56] [60] [61] [62] [63] [76] [79]
57	Filiep J. Vanpoucke	[13]
58	Ana Lucia Varbanescu	[86]
59	Stamatis Vassiliadis	[47]
60	Alle-Jan van der Veen	[7] [10] [49]
61	Ingrid Verbauwhede	[75]
62	Kees A. Vissers	[22] [25] [36] [44]
63	Richard L. Walke	[41] [42]
64	Pieter van der Wolf	[22] [25] [36] [38] [39] [40] [44] [51]
65	Roger Woods (Roger F. Woods)	[75]
66	Huimin Yang	[24]
67	A. C. Yilmaz	[5]
68	Claudiu Zissulescu	[50] [59] [60] [64] [65] [68] [74] [79] [84]
69	Vladimir D. Zivkovic	[51]

Colors in the list of coauthors

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