Rahul B. Deokar

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1996

3 Sachin S. Sapatnekar, Rahul B. Deokar: Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1237-1248 (1996)

1995

2 Rahul B. Deokar, Sachin S. Sapatnekar: A Fresh Look at Retiming Via Clock Skew Optimization. DAC 1995: 310-315

1994

1 Rahul B. Deokar, Sachin S. Sapatnekar: A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS 1994: 407-410

	1996
3		Sachin S. Sapatnekar, Rahul B. Deokar: Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1237-1248 (1996)
	1995
2		Rahul B. Deokar, Sachin S. Sapatnekar: A Fresh Look at Retiming Via Clock Skew Optimization. DAC 1995: 310-315
	1994
1		Rahul B. Deokar, Sachin S. Sapatnekar: A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS 1994: 407-410

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