Jean-Luc Dekeyser

	2011
87		Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser: FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. DASIP 2011: 269-276
86		Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser: High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. DASIP 2011: 308-315
85		Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser: Fast and accurate hybrid power estimation methodology for embedded systems. DASIP 2011: 45-51
84		Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser: Hybrid system level power consumption estimation for FPGA-based MPSoC. ICCD 2011: 239-246
83		Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser: A model-driven based framework for rapid parallel SoC FPGA prototyping. International Symposium on Rapid System Prototyping 2011: 149-155
82		George Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio: A prototyping environment for high performance reconfigurable computing. ReCoSoC 2011: 1-8
81		Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Rabie Ben Atitallah, Anne Etien, Philippe Marquet, Jean-Luc Dekeyser: A Model-Driven Design Framework for Massively Parallel Embedded Systems. ACM Trans. Embedded Comput. Syst. 10(4): 39 (2011)
80		Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser: Programming Massively Parallel Architectures using MARTE: a Case Study CoRR abs/1103.4881: (2011)
79		Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser: A Modeling Approach based on UML/MARTE for GPU Architecture CoRR abs/1105.4424: (2011)
78		Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser, Yvonnick Le Menach: Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines CoRR abs/1107.0538: (2011)
77		Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai: A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. EURASIP J. Emb. Sys. 2011: (2011)
76		Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser: Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture. Technique et Science Informatiques 30(9): 1089-1113 (2011)
	2010
75		Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid: Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. ARC 2010: 110-121
74		Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser: Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. DASIP 2010: 68-75
73		Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser: Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD 2010: 706-713
72		Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser: IP Based Configurable SIMD Massively Parallel SoC. FPL 2010: 247-250
71		Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki: A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. ISSPIT 2010: 528-531
70		Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser: Traceability for Mutation Analysis in Model Transformation. MoDELS Workshops 2010: 259-273
69		Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Yvonnick Le Menach, Jean-Luc Dekeyser: Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines CoRR abs/1010.4639: (2010)
68		Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser: Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. IJES 4(3/4): 204-224 (2010)
67		Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid: Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. Journal of Systems Architecture - Embedded Systems Design 56(7): 278-292 (2010)
	2009
66		Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser: Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. AICCSA 2009: 368-373
65		Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser: Model-Driven Design of Embedded Multimedia Applications on SoCs. DSD 2009: 207-210
64		Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. DSD 2009: 3-10
63		Yassine Aydi, Ramzi Tligue, Maissa Elleuch, Mohamed Abid, Jean-Luc Dekeyser: A multi level functional verification of multistage interconnection network for MPSOC. ICECS 2009: 439-442
62		Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser: Traceability Mechanism for Error Localization in Model Transformation. ICSOFT (1) 2009: 66-73
	2008
61		Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser: An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. ASAP 2008: 126-131
60		Sebastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser: Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. DIPES 2008: 69-78
59		Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser: MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. ESTImedia 2008: 47-52
58		Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser: MARTE-based Design of a Multimedia Application and Formal Analysis. FDL 2008: 160-166
57		Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser: Using an MDE Approach for Modeling of Interconnection Networks. ISPAN 2008: 289-294
56		Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser: Modeling and Formal Validation of High-Performance Embedded Systems. ISPDC 2008: 215-222
55		Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser: A Graphical Framework for High Performance Computing Using An MDE Approach. PDP 2008: 165-173
54		Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser: Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP J. Emb. Sys. 2008: (2008)
53		Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser: Safe design of high-performance embedded systems in an MDE framework. ISSE 4(3): 215-222 (2008)
	2007
52		Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser: Massively parallel processing on a chip. Conf. Computing Frontiers 2007: 277-286
51		Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser: Model Transformations from a Data Parallel Formalism towards Synchronous Languages. FDL 2007: 255-260
50		Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser: MARTE: UML-based Hardware Design from Modelling to Simulation. FDL 2007: 274-279
49		Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser: A Design Flow to Map Parallel Applications onto FPGAs. FPL 2007: 605-608
48		Éric Piel, Philippe Marquet, Jean-Luc Dekeyser: Model Transformations for the Compilation of Multi-processor Systems-on-Chip. GTTSE 2007: 459-473
47		Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser: An MPSoC Performance Estimation Framework Using Transaction Level Modeling. RTCSA 2007: 525-533
46		Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser: Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC 2007: 90-97
45		Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser: An Open Framework for Detailed Hardware Modeling. SIES 2007: 118-125
	2006
44		Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser: Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS 2006: 298-310
43		Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser: FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. DSD 2006: 280-287
42		Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet: UML2 Profile for Modeling Controlled Data Parallel Applications. FDL 2006: 359-367
41		Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser: Real-time systems for multiprocessor architectures. IPDPS 2006
40		Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser: Safe Design Methodology for an Intelligent Cruise Control System with GPS. VTC Fall 2006: 1-5
39		Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson: A universal performance factor for multi-criteria evaluation of multistage interconnection networks. Future Generation Comp. Syst. 22(7): 794-804 (2006)
	2005
38		J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser: Embed Scripting inside SystemC. FDL 2005: 373-385
37		Lossan Bonde, Pierre Boulet, Jean-Luc Dekeyser: Traceability and Interoperability in Models Transformations. FDL 2005: 543-555
36		Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet: Mode-Automata Based Methodology for Scade. HSCC 2005: 386-401
35		Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson: Scalable Multistage Network for Multiprocessor System-on-Chip Design. ISPAN 2005: 352-357
34		Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet: Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. MoDELS 2005: 445-459
33		Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser: Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. PPAM 2005: 896-903
32		Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena: Model Driven Engineering for Regular MPSoC Co-design. ReCoSoC 2005: 129-136
	2004
31		Lossan Bonde, Cédric Dumoulin, Jean-Luc Dekeyser: Metamodels and MDA Transformations for Embedded Systems. FDL 2004: 240-252
30		Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser: Regular Hardware Architecture Modeling with UML2. FDL 2004: 289-301
29		E. Turbatu, Samy Meftali, Smaïl Niar, Jean-Luc Dekeyser: An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). FDL 2004: 378-380
28		M. Samyn, Samy Meftali, Jean-Luc Dekeyser: MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. FDL 2004: 452-463
27		Samy Meftali, Jean-Luc Dekeyser: An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. IWSOC 2004: 55-58
26		Ahmad Chadi Aljundi, Jean-Luc Dekeyser: The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. PDP 2004: 72-
25		Samy Meftali, Jean-Luc Dekeyser: SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. Virtual Enterprises and Collaborative Networks 2004: 387-394
	2003
24		Cédric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, S. Pulon, G. Cristau: Interoperability between Design and Simulation Tools using Model Transformation Techniques. FDL 2003: 274-285
23		Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet: MDA for SoC Design, Intensive Signal Processing Experiment. FDL 2003: 309-317
22		Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson: A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks. IPDPS 2003: 277
21		Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Isaac D. Scherson: An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks. ISCA PDCS 2003: 1-8
20		Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, T. Theeuwen: Distributed Process Networks - Using Half FIFO Queues in CORBA. PARCO 2003: 31-38
	2002
19		Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet: GASPARD - A Visual Parallel Programming Environment. PARELEC 2002: 145-150
	2001
18		Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure: Visual Data-Parallel Programming for Signal Processing Applications. PDP 2001: 105-112
17		Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser: Compilation Principle of a Specification Language Dedicated to Signal Processing. PaCT 2001: 358-370
	2000
16		Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, Georges Marques: Parallelization of a 3D Magnetostatic Code Using High Performance Fortran. PARELEC 2000: 181-185
15		Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, Stéphane Clénet: High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns. VECPAR 2000: 519-528
	1998
14		Fabien Banse, Jean-Luc Dekeyser, Renaud Fauquembergue, François Dessenne: Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures. HPCN Europe 1998: 193-202
13		Dominique Sueur, Jean-Luc Dekeyser, Philippe Marquet: DPFS: A Data-Parallel File System Environment. HPCN Europe 1998: 940-942
12		Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser: Data-Parallel Load Balancing Strategies. Parallel Computing 24(11): 1665-1684 (1998)
	1997
11		Jean-Luc Dekeyser, Dominique Sueur: Data Parallel File System. PPSC 1997
10		Jean-Luc Dekeyser, Christian Lefebvre: Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder. PPSC 1997
9		M. Tahar Kechadi, Jean-Luc Dekeyser: Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems. Parallel Computing 23(13): 1963-1986 (1997)
	1996
8		Dominique Sueur, Jean-Luc Dekeyser: Dynamic Redistribution on Heterogeneous Parallel Computers. Euro-Par, Vol. I 1996: 173-177
7		Jean-Luc Dekeyser, Philippe Marquet: Supporting Irregular and Dynamic Computations in Data Parallel Languages. The Data Parallel Programming Model 1996: 197-219
6		Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire, Philippe Marquet: Irregular Data-Parallel Objects in C++. VECPAR 1996: 65-80
	1994
5		Cyril Fonlupt, Jean-Luc Dekeyser, Philippe Marquet: Dynamic Load Balancing on SIMD Data-Parallel Computers. EUROSIM 1994: 219-226
4		Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser: A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. HPCN 1994: 338-343
3		Jean-Luc Dekeyser, Dominique Lazure, Philippe Marquet: A Geometrical Data-Parallel Language. SIGPLAN Notices 29(4): 31-40 (1994)
	1993
2		Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet: HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. HCI (2) 1993: 591-596
	1990
1		Jean-Luc Dekeyser, Philippe Marquet, Ph. Pruex: EVA: an explicit vector language. SIGPLAN Notices 25(8): 53-71 (1990)

Coauthor Index

1	Adolf Abdallah	[58] [65] [76]
2	Mohamed Abid	[63] [64] [66] [67] [72] [75] [83]
3	George Afonso	[82]
4	Ahmad Chadi Aljundi	[21] [22] [26] [39]
5	Abdelkader Amar	[20]
6	Manel Ammar	[83]
7	Vincent Aranega	[62] [70]
8	Rabie Ben Atitallah	[44] [47] [64] [77] [81] [82] [84] [85]
9	Brahim Attia	[87]
10	Yassine Aydi	[63] [67]
11	Mouna Baklouti	[66] [67] [72] [75] [83]
12	Fabien Banse	[14]
13	Nicolas Bélanger	[82]
14	Akram-Djellal Benalia	[2]
15	Sébastien Le Beux	[43] [46] [49] [52] [81]
16	Lossan Bonde	[31] [37]
17	Pierre Boulet	[15] [16] [18] [19] [20] [23] [30] [32] [34] [36] [37] [42] [54] [56] [57]
18	Thomas Brandes	[15] [16]
19	Emmanuel Cagniot	[15] [16]
20	Luc Charest	[38]
21	Sana Cherif	[73] [86]
22	Hajer Chtioui	[64]
23	Stéphane Clénet	[15]
24	Alain Clouard	[60]
25	G. Cristau	[24]
26	Arnaud Cuccuru	[30] [32] [34]
27	Alain Demeure	[17] [18]
28	François Dessenne	[14]
29	Florent Devin	[19]
30	Cédric Dumoulin	[23] [24] [31]
31	Simon Duquennoy	[52]
32	Majdi Elhaji	[71] [87]
33	Yassin Elhillali	[61]
34	Maissa Elleuch	[63]
35	Anne Etien	[62] [70] [81]
36	Renaud Fauquembergue	[14]
37	Cyril Fonlupt	[4] [5] [12]
38	Abdoulaye Gamatié	[51] [53] [54] [56] [58] [65] [68] [76] [81]
39	Sébastien Gérard (Sebastien Gerard)	[45] [50] [60]
40	Alain Greiner	[44]
41	Frédéric Guyomarc'h	[55] [69] [78] [79] [80]
42	Abderrazek Jemai	[77]
43	M. Tahar Kechadi (Mohand Tahar Kechadi)	[9] [22] [39]
44	Jehangir Khan	[61]
45	Boris Kokoszko	[6] [24]
46	Ouassila Labbani	[36] [40] [42] [43]
47	Dominique Lazure	[3]
48	Christian Lefebvre	[10]
49	Jean-Luc Levaire	[6] [18]
50	Alexander Loyer	[82]
51	Georges Marques	[16]
52	Philippe Marquet	[1] [2] [3] [4] [5] [6] [7] [12] [13] [17] [18] [19] [23] [33] [34] [41] [43] [46] [48] [49] [52] [66] [67] [72] [75] [81] [83]
53	Ashish Meena	[32]
54	Samy Meftali	[25] [27] [28] [29] [35] [38] [44] [47] [52] [57] [59] [68] [71] [73] [74] [77] [86] [87]
55	Yvonnick Le Menach	[69] [78]
56	Jean-Marie Mottu	[62] [70]
57	Smaïl Niar	[29] [44] [47] [61] [64] [84] [85]
58	S. Penain	[38]
59	Éric Piel	[33] [41] [48] [81]
60	Francis Piriou	[15] [16]
61	Ph. Pruex	[1]
62	S. Pulon	[24]
63	Imran Rafiq Quadri	[57] [59] [68] [73] [74]
64	Ansgar Radermacher	[45] [50] [60]
65	Santhosh Kumar Rethinagiri	[84] [85]
66	Sebastien Revol	[60]
67	Atika Rivenq (Atika Rivenq-Menhaj, Atika Menhaj-Rivenq)	[61]
68	Antonio Wendell De Oliveira Rodrigues	[69] [78] [79] [80]
69	Martial Rubio	[82]
70	Éric Rutten	[40] [42] [51] [53] [54] [56] [68]
71	M. Samyn	[28]
72	Isaac D. Scherson	[21] [22] [35] [39]
73	Eric Senn	[84] [85]
74	Julien Soula	[17] [18] [33] [41]
75	Dominique Sueur	[8] [11] [13]
76	Safouan Taha	[45] [50] [60]
77	Julien Taillard	[55]
78	François Terrier	[60]
79	T. Theeuwen	[20]
80	Ramzi Tligue	[63]
81	Rached Tourki	[71] [87]
82	Chiraz Trabelsi	[77] [86]
83	E. Turbatu	[29]
84	J. Vennin	[38]
85	Huafeng Yu	[51] [53] [54] [56] [68]
86	Abdelkrim Zitouni	[71] [87]

Colors in the list of coauthors

Last update Mon Feb 13 22:11:03 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page