 | 2011 |
| 13 |  | Takahiro J. Yamaguchi,
Mohamed Abbas,
Mani Soma,
Takafumi Aoki,
Yasuo Furukawa,
Katsuhiko Degawa,
Satoshi Komatsu,
Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization.
ISCAS 2011: 2529-2532 |
| 12 |  | Takahiro J. Yamaguchi,
Mani Soma,
Takafumi Aoki,
Yasuo Furukawa,
Katsuhiko Degawa,
Kunihiro Asada,
Mohamed Abbas,
Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements.
ITC 2011: 1-10 |
| 2009 |
| 11 |  | Albert Tumewu,
Kazuyuki Miyazawa,
Takafumi Aoki,
Takahiro J. Yamaguchi,
Katsuhiko Degawa,
Takayuki Akita:
Phase-based alignment of two signals having partially overlapped spectra.
ICASSP 2009: 3337-3340 |
| 10 |  | Naofumi Homma,
Yuki Watanabe,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
Multiple-Valued Logic and Soft Computing 15(4): 329-340 (2009) |
| 2008 |
| 9 |  | Yuki Watanabe,
Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
ISMVL 2008: 112-117 |
| 2007 |
| 8 |  | Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
ISMVL 2007: 31 |
| 7 |  | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
Multiple-Valued Logic and Soft Computing 13(3): 249-266 (2007) |
| 6 |  | Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.
Multiple-Valued Logic and Soft Computing 13(4-6): 487-502 (2007) |
| 2006 |
| 5 |  | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Katsuhiko Nishiguchi,
Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2006: 19 |
| 2005 |
| 4 |  | Katsuhiko Degawa,
Takafumi Aoki,
Hiroshi Inokawa,
Tatsuo Higuchi,
Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2005: 32-38 |
| 2004 |
| 3 |  | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL 2004: 262-268 |
| 2 |  | Hiroshi Inokawa,
Yasuo Takahashi,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL 2004: 269-274 |
| 2003 |
| 1 |  | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
ISMVL 2003: 213-220 |