Debatosh Debnath

	2011
12		Debatosh Debnath: Synthesis of Easily Testable AND-EXOR Networks. I. J. Comput. Appl. 18(2): 123- (2011)
	2007
11		Debatosh Debnath, Tsutomu Sasao: A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks. IEICE Transactions 90-A(5): 932-940 (2007)
	2006
10		Debatosh Debnath, Tsutomu Sasao: Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries. IEICE Transactions 89-A(12): 3443-3450 (2006)
	2005
9		Debatosh Debnath, Tsutomu Sasao: Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs. IEICE Transactions 88-A(12): 3332-3341 (2005)
8		Debatosh Debnath, Tsutomu Sasao: Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders. IEICE Transactions 88-D(7): 1492-1500 (2005)
	2004
7		Debatosh Debnath, Tsutomu Sasao: Efficient computation of canonical form for Boolean matching in large libraries. ASP-DAC 2004: 591-596
	2003
6		Debatosh Debnath, Zvonko G. Vranesic: A fast algorithm for OR-AND-OR synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1166-1176 (2003)
	2000
5		Debatosh Debnath, Tsutomu Sasao: Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. ASP-DAC 2000: 247-252
	1999
4		Debatosh Debnath, Tsutomu Sasao: Fast Boolean Matching Under Permutation Using Representative. ASP-DAC 1999: 359-362
3		Debatosh Debnath, Tsutomu Sasao: Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. ISMVL 1999: 99-104
	1998
2		Debatosh Debnath, Tsutomu Sasao: A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. ASP-DAC 1998: 69-74
	1995
1		Debatosh Debnath, Tsutomu Sasao: GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. ASP-DAC 1995

Coauthor Index

1	Tsutomu Sasao	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11]
2	Zvonko G. Vranesic	[6]

Colors in the list of coauthors

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