Andrew DeOrio

	2012
16		Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen: A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 726-739 (2012)
	2011
15		Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh: DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. DAC 2011: 912-917
14		Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco: Post-silicon bug diagnosis with inconsistent executions. ICCAD 2011: 755-761
13		Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco: Functional correctness for CMP interconnects. ICCD 2011: 352-359
12		Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco: ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT 2011: 298-309
11		Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. 16(3): 30 (2011)
	2010
10		Andrew DeOrio, Valeria Bertacco: Electronic design automation for social networks. DAC 2010: 621-622
	2009
9		Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: Event-driven gate-level simulation with GP-GPUs. DAC 2009: 557-562
8		Andrew DeOrio, Valeria Bertacco: Human computing for EDA. DAC 2009: 621-622
7		David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817
6		Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: GCS: High-performance gate-level simulation with GPGPUs. DATE 2009: 1332-1337
5		David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26
4		Andrew DeOrio, Ilya Wagner, Valeria Bertacco: Dacota: Post-silicon validation of the memory subsystem in multi-core designs. HPCA 2009: 405-416
3		Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen: Inferno: Streamlining Verification With Inferred Semantics. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 728-741 (2009)
	2008
2		Andrew DeOrio, Adam Bauserman, Valeria Bertacco: Post-silicon verification for cache coherence. ICCD 2008: 348-355
	2007
1		Andrew DeOrio, Adam Bauserman, Valeria Bertacco: Chico: An On-chip Hardware Checker for Pipeline Control Logic. MTV 2007: 91-97

Coauthor Index

1	Rawan Abdel-Khalek	[13]
2	Konstantinos Aisopos	[12] [15]
3	Adam Bauserman	[1] [2] [3]
4	Valeria Bertacco	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
5	David Blaauw (David T. Blaauw)	[5] [7] [16]
6	Debapriya Chatterjee	[6] [9] [11]
7	Gregory K. Chen	[5] [16]
8	David Fick	[5] [7] [16]
9	Jin Hu	[7] [16]
10	Beth Isaksen	[3]
11	Daya Shanker Khudia	[14]
12	Ritesh Parikh	[13]
13	Li-Shiuan Peh	[12] [15]
14	Dennis Sylvester	[5] [7] [16]
15	Ilya Wagner	[4]

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