Azadeh Davoodi

	2012
52		Min Li, Azadeh Davoodi, Mohammad Tehranipoor: A sensor-assisted self-authentication framework for hardware trojan detection. DATE 2012: 1331-1336
51		Min Li, Azadeh Davoodi, Lin Xie: Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. DATE 2012: 1591-1596
	2011
50		Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth: Power-driven global routing for multi-supply voltage domains. DATE 2011: 443-448
49		Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth: Congestion analysis for global routing via integer programming. ICCAD 2011: 256-262
48		Lin Xie, Azadeh Davoodi: Bound-Based Statistically-Critical Path Extraction Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 59-71 (2011)
47		Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth: GRIP: Global Routing via Integer Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 72-84 (2011)
	2010
46		Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu: Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC 2010: 593-599
45		Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth: A parallel integer programming approach to global routing. DAC 2010: 194-199
44		Lin Xie, Azadeh Davoodi, Kewal K. Saluja: Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. DAC 2010: 274-279
43		Lin Xie, Azadeh Davoodi: Representative path selection for post-silicon timing prediction under variability. DAC 2010: 386-391
42		Hamid Shojaei, Azadeh Davoodi: Trace signal selection to enhance timing and logic visibility in post-silicon validation. ICCAD 2010: 168-172
41		Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten: A pareto-algebraic framework for signal power optimization in global routing. ISLPED 2010: 407-412
	2009
40		Lin Xie, Azadeh Davoodi: Bound-based identification of timing-violating paths under variability. ASP-DAC 2009: 278-283
39		Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth: GRIP: scalable 3D global routing using integer programming. DAC 2009: 320-325
38		Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim: Statistical static timing analysis considering leakage variability in power gated designs. ISLPED 2009: 57-62
37		Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar: False Path Aware Timing Yield Estimation under Variability. VTS 2009: 161-166
36		Tai-Hsuan Wu, Azadeh Davoodi: PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1666-1678 (2009)
35		Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu: Adjustment-Based Modeling for Timing Analysis Under Variability. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1085-1095 (2009)
	2008
34		Tai-Hsuan Wu, Azadeh Davoodi: PaRS: fast and near-optimal grid-based cell sizing for library-based design. ICCAD 2008: 107-111
33		Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu: Adjustment-based modeling for statistical static timing analysis with high dimension of variability. ICCAD 2008: 181-184
32		Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi: SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. ICCD 2008: 551-556
31		Jungseob Lee, Lin Xie, Azadeh Davoodi: A Dual-Vt low leakage SRAM array robust to process variations. ISCAS 2008: 580-583
30		Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi: A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ISLPED 2008: 45-50
29		Lin Xie, Azadeh Davoodi: Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. ISQED 2008: 156-161
28		Lin Xie, Azadeh Davoodi: Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. ISQED 2008: 712-717
27		Azadeh Davoodi, Ankur Srivastava: Variability Driven Gate Sizing for Binning Yield Optimization. IEEE Trans. VLSI Syst. 16(6): 683-692 (2008)
26		Lin Xie, Azadeh Davoodi: Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2264-2276 (2008)
25		Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi: A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. J. Low Power Electronics 4(2): 191-201 (2008)
	2007
24		Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Statistical timing analysis using Kernel smoothing. ICCD 2007: 97-102
23		Jungseob Lee, Azadeh Davoodi: Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. ISCAS 2007: 3018-3021
22		Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design 2007: 571-576
	2006
21		Azadeh Davoodi, Ankur Srivastava: Variability driven gate sizing for binning yield optimization. DAC 2006: 959-964
20		Azadeh Davoodi, Ankur Srivastava: Probabilistic evaluation of solutions in variability-driven optimization. ISPD 2006: 17-24
19		Azadeh Davoodi, Ankur Srivastava: Effective techniques for the generalized low-power binding problem. ACM Trans. Design Autom. Electr. Syst. 11(1): 52-69 (2006)
18		Li Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal: FPGA Dynamic Power Minimization through Placement and Routing Constraints. EURASIP J. Emb. Sys. 2006: (2006)
17		Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3010-3016 (2006)
16		Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: A statistical methodology for wire-length prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1327-1336 (2006)
	2005
15		Azadeh Davoodi, Ankur Srivastava: Simultaneous floorplanning and resource binding: a probabilistic approach. ASP-DAC 2005: 517-522
14		Azadeh Davoodi, Ankur Srivastava: Wake-up protocols for controlling current surges in MTCMOS-based technology. ASP-DAC 2005: 868-871
13		Azadeh Davoodi, Ankur Srivastava: Variability-Driven Buffer Insertion Considering Correlations. ICCD 2005: 425-430
12		Azadeh Davoodi, Ankur Srivastava: Probabilistic dual-Vth leakage optimization under variability. ISLPED 2005: 143-148
11		Azadeh Davoodi, Ankur Srivastava: Voltage scheduling under unpredictabilities: a risk management paradigm. ACM Trans. Design Autom. Electr. Syst. 10(2): 354-368 (2005)
10		Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Simultaneous V/sub t/ selection and assignment for leakage optimization. IEEE Trans. VLSI Syst. 13(6): 762-765 (2005)
9		Azadeh Davoodi, Ankur Srivastava: Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. IEEE Trans. VLSI Syst. 13(8): 934-942 (2005)
	2004
8		Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI 2004: 13-18
7		Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Variability inspired implementation selection problem. ICCAD 2004: 423-427
6		Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Efficient statistical timing analysis through error budgeting. ICCAD 2004: 473-477
5		Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Wire-length prediction using statistical techniques. ICCAD 2004: 702-705
4		Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Empirical models for net-length probability distribution and applications. IEEE Trans. VLSI Syst. 12(10): 1066-1075 (2004)
	2003
3		Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava: A Probabilistic Approach to Buffer Insertion. ICCAD 2003: 560-567
2		Azadeh Davoodi, Ankur Srivastava: Effective graph theoretic techniques for the generalized low power binding problem. ISLPED 2003: 152-157
1		Azadeh Davoodi, Ankur Srivastava: Voltage scheduling under unpredictabilities: a risk management paradigm. ISLPED 2003: 302-305

Coauthor Index

1	Deepak Agarwal	[18]
2	Michael J. Anderson	[38]
3	Twan Basten	[41]
4	Charlie Chung-Ping Chen (Chung-Ping Chen)	[46]
5	Ashish Dobhal	[22]
6	Matthew French	[18]
7	Yu Hen Hu	[46]
8	Vishal Khandelwal	[3] [4] [5] [6] [7] [8] [10] [16] [17] [22] [24]
9	Nam Sung Kim	[38] [46]
10	Anuj Kumar	[32]
11	Jungseob Lee	[23] [31] [38]
12	Min Li	[51] [52]
13	Jeff T. Linderoth (Jeffrey T. Linderoth, Jeff Linderoth)	[39] [45] [47] [49] [50]
14	Akash Nanavati	[3]
15	Dongkeun Oh	[46]
16	Miodrag Potkonjak	[5] [16] [24]
17	Kewal K. Saluja	[37] [44]
18	Hamid Shojaei	[41] [42] [49]
19	Abhishek A. Sinkar	[37] [38]
20	Ankur Srivastava	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [20] [21] [22] [24] [27]
21	Mohammad Tehranipoor	[52]
22	Li Wang	[18]
23	Jennifer L. Wong	[5] [16] [24]
24	Tai-Hsuan Wu	[25] [30] [32] [33] [34] [35] [36] [39] [41] [45] [47] [50]
25	Lin Xie	[25] [26] [28] [29] [30] [31] [33] [35] [37] [40] [43] [44] [48] [51]
26	Jun Zhang	[33] [35]

Colors in the list of coauthors

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