Ramyanshu Datta

	2010
12		Ramyanshu Datta, Mahit Warhadpande, Dale Heaton, S. Aarthi, Ram Jonnavithula: Case studies of mixed-signal DFT. ISQED 2010: 582-589
11		Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham: On-Chip Delay Measurement Based Response Analysis for Timing Characterization. J. Electronic Testing 26(6): 599-619 (2010)
	2009
10		Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta: A novel architecture for on-chip path delay measurement. ITC 2009: 1-10
	2008
9		Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta: Path-RO: a novel on-chip critical path delay measurement under process variations. ICCAD 2008: 640-646
8		Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Performance-Optimized Design for Parametric Reliability. J. Electronic Testing 24(1-3): 129-141 (2008)
7		Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Controllability of Static CMOS Circuits for Timing Characterization. J. Electronic Testing 24(5): 481-496 (2008)
	2006
6		Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11
5		Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham: A Scheme for On-Chip Timing Characterization. VTS 2006: 24-29
	2005
4		Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham: Testing and debugging delay faults in dynamic circuits. ITC 2005: 10
	2004
3		Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham: On-chip delay measurement for silicon debug. ACM Great Lakes Symposium on VLSI 2004: 145-148
2		Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480
1		Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127

Coauthor Index

1	S. Aarthi	[12]
2	Jacob A. Abraham	[1] [2] [3] [4] [5] [6] [7] [8] [11]
3	Wendy Belluomini	[2]
4	Gary D. Carpenter	[5] [11]
5	Abhijit Chatterjee	[6] [8]
6	Abdulkadir Utku Diril	[6] [8]
7	Ravi Gupta	[1] [7]
8	Dale Heaton	[12]
9	Ram Jonnavithula	[12]
10	Jente B. Kuang	[2]
11	Chandler McDowell	[2]
12	Robert K. Montoye	[2] [4]
13	Sani R. Nassif	[4]
14	Hung C. Ngo	[2]
15	Kevin J. Nowka	[2] [5] [6] [8] [11]
16	Ashwin Raghunathan	[3] [11]
17	Antony Sebastine	[1] [3] [7] [11]
18	Mohammad Tehranipoor	[9] [10]
19	Xiaoxiao Wang	[9] [10]
20	Mahit Warhadpande	[12]
21	Manuel A. d'Abreu	[1] [7]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page