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Sudeb Dasgupta Coauthor index pubzone.org

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DBLP keys2012
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNaushad Alam, Bulusu Anand, Sudeb Dasgupta: Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED 2012: 717-722
2011
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRamesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. ISVLSI 2011: 37-42
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRamesh Vaddi, R. P. Agarwal, Sudeb Dasgupta: Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. Microelectronics Journal 42(5): 798-807 (2011)
2010
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRamesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. J. Low Power Electronics 6(1): 103-114 (2010)
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRamesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. Microelectronics Journal 41(4): 195-211 (2010)
2009
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMaruthi Chandrasekhar Bh, Sudeb Dasgupta: A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. ISQED 2009: 447-450
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRamesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. VLSI Design 2009: (2009)
2008
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDeblina Sarkar, Deepanjan Datta, Sudeb Dasgupta: Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design. JCP 3(2): 37-47 (2008)
2007
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDeblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta: Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. VLSI Design 2007: 183-188
2006
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDeepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta: Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Microelectronics Journal 37(6): 537-545 (2006)

Coauthor Index

1R. P. Agarwal [4] [6] [7] [8] [9]
2Naushad Alam [10]
3Bulusu Anand [10]
4Maruthi Chandrasekhar Bh [5]
5Deepanjan Datta [1] [2] [3]
6Samiran Ganguly [2]
7A. Ananda Prasad Sarab [1] [2]
8Deblina Sarkar [2] [3]
9Ramesh Vaddi [4] [6] [7] [8] [9]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page