 | 2012 |
| 10 |  | Naushad Alam,
Bulusu Anand,
Sudeb Dasgupta:
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.
ISQED 2012: 717-722 |
| 2011 |
| 9 |  | Ramesh Vaddi,
Sudeb Dasgupta,
R. P. Agarwal:
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET.
ISVLSI 2011: 37-42 |
| 8 |  | Ramesh Vaddi,
R. P. Agarwal,
Sudeb Dasgupta:
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options.
Microelectronics Journal 42(5): 798-807 (2011) |
| 2010 |
| 7 |  | Ramesh Vaddi,
Sudeb Dasgupta,
R. P. Agarwal:
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs.
J. Low Power Electronics 6(1): 103-114 (2010) |
| 6 |  | Ramesh Vaddi,
Sudeb Dasgupta,
R. P. Agarwal:
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.
Microelectronics Journal 41(4): 195-211 (2010) |
| 2009 |
| 5 |  | Maruthi Chandrasekhar Bh,
Sudeb Dasgupta:
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications.
ISQED 2009: 447-450 |
| 4 |  | Ramesh Vaddi,
Sudeb Dasgupta,
R. P. Agarwal:
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications.
VLSI Design 2009: (2009) |
| 2008 |
| 3 |  | Deblina Sarkar,
Deepanjan Datta,
Sudeb Dasgupta:
Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design.
JCP 3(2): 37-47 (2008) |
| 2007 |
| 2 |  | Deblina Sarkar,
Samiran Ganguly,
Deepanjan Datta,
A. Ananda Prasad Sarab,
Sudeb Dasgupta:
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.
VLSI Design 2007: 183-188 |
| 2006 |
| 1 |  | Deepanjan Datta,
A. Ananda Prasad Sarab,
Sudeb Dasgupta:
Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET.
Microelectronics Journal 37(6): 537-545 (2006) |