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P. S. Dasgupta
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 34 | Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta: A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip. VLSI Design 2012: 227-232 | |
| 33 | Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta: Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips. Integration 45(3): 316-330 (2012) | |
| 2011 | ||
| 32 | Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta: Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2011: 229-234 | |
| 31 | Prasun Ghosal, Hafizur Rahaman, Satrajit Das, Arindam Das, Parthasarathi Dasgupta: Obstacle Aware Routing in 3D Integrated Circuits. ADCONS 2011: 451-460 | |
| 30 | Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta: A Multi-pin Droplet Routing Algorithm for Digital Microfluidic Biochips. BIODEVICES 2011: 216-223 | |
| 29 | Tuhina Samanta, Sanoara Khatun, Hafizur Rahaman, Parthasarathi Dasgupta: Crosstalk aware coupled line delay tree construction for on-chip interconnects. ISQED 2011: 353-358 | |
| 28 | Pranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta: A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. ISVLSI 2011: 317-318 | |
| 27 | Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Near-optimal Y-routed delay trees in nanometric interconnect design. IET Computers & Digital Techniques 5(1): 36-48 (2011) | |
| 2010 | ||
| 26 | Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta: A novel droplet routing algorithm for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2010: 441-446 | |
| 25 | Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Minimizing Thermal Disparities during Placement in 3D ICs. CSE 2010: 160-167 | |
| 2009 | ||
| 24 | Raju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen-Sarma: An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking. SBCCI 2009 | |
| 23 | Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta: A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. VLSI Design 2009: 387-392 | |
| 22 | Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay: MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9(2): 711-724 (2009) | |
| 2008 | ||
| 21 | Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. ISVLSI 2008: 369-374 | |
| 20 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Revisiting fidelity: a case of elmore-based Y-routing trees. SLIP 2008: 27-34 | |
| 2007 | ||
| 19 | Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma: A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA 2007: 111-116 | |
| 18 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Minimum-Congestion Placement for Y-interconnects: Some studies and observations. ISVLSI 2007: 73-80 | |
| 2006 | ||
| 17 | Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta: Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT 2006: 281-284 | |
| 16 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. ISCAS 2006 | |
| 15 | Parthasarathi Dasgupta, Prashant Yadava: Linear Required-Arrival-Time Trees and their Construction. VLSI Design 2006: 790-793 | |
| 2005 | ||
| 14 | Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. IICAI 2005: 232-251 | |
| 13 | Parthasarathi Dasgupta: Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions. VLSI Design 2005: 615-620 | |
| 2004 | ||
| 12 | Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah: Physical Design Trends and Layout-Based Fault Modeling. VLSI Design 2004: 6-8 | |
| 2003 | ||
| 11 | Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu: A Novel Metric for Interconnect Architecture Performance. DATE 2003: 10448-10455 | |
| 10 | Parthasarathi Dasgupta: Range-Based Discrepancy Search with Applications to VLSI Design. IICAI 2003: 621-631 | |
| 2002 | ||
| 9 | Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya: Monotone bipartitioning problem in a planar point set with applications to VLSI. ACM Trans. Design Autom. Electr. Syst. 7(2): 231-248 (2002) | |
| 2001 | ||
| 8 | Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta: Partitioning Routing Area into Zones with Distinct Pins. VLSI Design 2001: 345- | |
| 7 | Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicible rectangular graphs and their optimal floorplans. ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001) | |
| 6 | Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya: Searching networks with unrestricted edge costs. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 497-507 (2001) | |
| 1998 | ||
| 5 | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and optimal sizing of floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 126-135 (1998) | |
| 1997 | ||
| 4 | Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155 | |
| 1996 | ||
| 3 | Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya: Geometric bipartitioning problem and its applications to VLSI. VLSI Design 1996: 400-405 | |
| 1995 | ||
| 2 | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715 | |
| 1 | P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: VLSI floorplan generation and area optimization using AND-OR graph search. VLSI Design 1995: 370-375 | |
| 1 | Sanghamitra Bandyopadhyay | [17] [22] |
| 2 | Indrajit Banerjee | [34] |
| 3 | Bhargab B. Bhattacharya | [1] [2] [3] [5] [6] [8] [9] [12] |
| 4 | Arindam Das | [31] |
| 5 | Satrajit Das | [31] |
| 6 | Prasun Ghosal | [14] [16] [18] [20] [21] [23] [25] [31] |
| 7 | Raju Halder | [24] |
| 8 | Andrew B. Kahng | [11] |
| 9 | Sanoara Khatun | [29] |
| 10 | Rajesh Mandal | [28] |
| 11 | Swamy Muddu | [11] |
| 12 | Ritwik Mukherjee | [34] |
| 13 | Subhas C. Nandy | [3] [6] [9] |
| 14 | Saptarshi Naskar | [24] |
| 15 | Peichen Pan | [9] |
| 16 | Hafizur Rahaman | [14] [16] [18] [20] [21] [23] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] |
| 17 | Pranab Roy | [26] [28] [30] [32] [33] |
| 18 | Debasri Saha | [19] |
| 19 | Sriparna Saha | [17] [22] |
| 20 | Tuhina Samanta | [14] [16] [18] [20] [21] [23] [27] [29] [34] |
| 21 | Anup K. Sen | [3] [6] |
| 22 | Samar Sen-Sarma | [19] [24] |
| 23 | Koushik Sinha | [8] |
| 24 | Susmita Sur-Kolay | [1] [2] [4] [5] [7] [8] [12] [17] [19] [22] |
| 25 | Prashant Yadava | [15] |
| 26 | Sujit T. Zachariah | [12] |
Colors in the list of coauthors
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