Reetuparna Das

	2011
12		Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. IEEE Micro 31(1): 29-41 (2011)
11		Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das: RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distrib. Comput. 71(5): 625-640 (2011)
	2010
10		Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li: Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155
9		Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Aérgia: exploiting packet latency slack in on-chip networks. ISCA 2010: 106-116
	2009
8		Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186
7		Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Application-aware prioritization mechanisms for on-chip networks. MICRO 2009: 280-291
6		Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das: A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303
5		Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir: A case for integrated processor-cache partitioning in chip multiprocessors. SC 2009
	2008
4		Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das: Performance and power optimization through data compression in Network-on-Chip architectures. HPCA 2008: 215-225
3		Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261
	2007
2		Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das: Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects 2007: 15-20
1		Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149

Coauthor Index

1	Chita R. Das	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
2	Xiangyu Dong	[10]
3	Soumya Eachempati	[3] [6] [8] [11]
4	Ravi R. Iyer (Ravishankar R. Iyer)	[2] [4] [6] [11]
5	Mahmut T. Kandemir	[5]
6	Jongman Kim	[1] [2]
7	Jian Li	[10]
8	Asit K. Mishra	[3] [4] [5] [6] [8] [11]
9	Thomas Moscibroda	[7] [9] [12]
10	Onur Mutlu	[7] [9] [12]
11	Chrysostomos Nicopoulos	[1] [2] [4]
12	Dongkook Park	[1] [2] [3] [4]
13	Shekhar Srikantaiah	[5]
14	Guangyu Sun	[10]
15	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[1] [2] [3] [4] [6] [8] [11]
16	Xiaoxia Wu	[10]
17	Yuan Xie	[1] [3] [10]
18	Aditya Yanamandra	[11]
19	Mazin S. Yousif	[1] [4]

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