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Koushik K. Das Coauthor index pubzone.org

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DBLP keys2009
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das: Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD 2009: 631-636
2008
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoushik K. Das, Ching-Te Chuang, Richard B. Brown: Reducing parasitic BJT effects in partially depleted SOI digital logic circuits. Microelectronics Journal 39(2): 275-285 (2008)
2006
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoushik K. Das, Shih-Hsien Lo, Ching-Te Chuang: High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. VLSI Design 2006: 758-761
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLScott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
2004
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang: Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107
2003
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown: New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoushik K. Das, Richard B. Brown: Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. ISVLSI 2003: 29-34
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoushik K. Das, Richard B. Brown: Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. VLSI Design 2003: 291-296

Coauthor Index

1Emrah Acar [8]
2Aditya Bansal [8]
3Kerry Bernstein [5]
4David Blaauw (David T. Blaauw) [5]
5Richard B. Brown [1] [2] [3] [7]
6Andres Bryant [5]
7Leland Chang [5]
8Ching-Te Chuang [3] [4] [6] [7] [8]
9Peter W. Cook [3]
10Wilfried Haensch [5]
11Scott Hanson [5]
12Fook-Luen Heng [8]
13Rajiv V. Joshi [3] [4]
14Rouwaida Kanj [8]
15Keunwoo Kim [4] [8]
16Jin-Fuw Lee [8]
17Shih-Hsien Lo [6]
18Saibal Mukhopadhyay [8]
19Sani R. Nassif [8]
20Edward J. Nowak [5]
21Rama N. Singh [8]
22Amith Singhee [8]
23Dennis Sylvester [5]
24Bo Zhai [5]

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