Debesh Kumar Das

Debesh K. Das

	2011
37		Hafizur Rahaman, Dipak K. Kole, Debesh K. Das, Bhargab B. Bhattacharya: Fault diagnosis in reversible circuits under missing-gate fault model. Computers & Electrical Engineering 37(4): 475-485 (2011)
	2010
36		Dipak K. Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2010: 33-38
	2009
35		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Testable design of AND-EXOR logic networks with universal test sets. Computers & Electrical Engineering 35(5): 644-658 (2009)
	2008
34		Hafizur Rahaman, Dipak K. Kole, Debesh Kumar Das, Bhargab B. Bhattacharya: On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design 2008: 163-168
33		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. IEEE T. Instrumentation and Measurement 57(12): 2838-2845 (2008)
	2006
32		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electronic Testing 22(2): 125-142 (2006)
	2005
31		Hafizur Rahaman, Debesh K. Das: Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC 2005: 172-177
30		Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das: Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium 2005: 398-403
29		Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das: Cellular Automata Based Test Structures with Logic Folding. VLSI Design 2005: 71-74
28		Biplab K. Sikdar, Samir Roy, Debesh K. Das: A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electronic Testing 21(1): 83-93 (2005)
	2004
27		Hafizur Rahaman, Debesh K. Das: A Simple Delay Testable Synthesis of Symmetric Functions. AACC 2004: 263-270
26		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC 2004: 224-229
25		Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara: Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium 2004: 342-347
24		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design 2004: 487-492
23		Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian: Design & Test Education in Asia. IEEE Design & Test of Computers 21(4): 331-338 (2004)
22		Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electronic Testing 20(3): 315-323 (2004)
	2003
21		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium 2003: 284-289
	2002
20		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: A New Synthesis of Symmetric Functions. VLSI Design 2002: 160-165
19		Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das: Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. VLSI Design 2002: 671-676
18		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. 17(6): 731-737 (2002)
	2001
17		Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri: Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324
16		Biplab K. Sikdar, Samir Roy, Debesh K. Das: Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium 2001: 285-
15		Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara: Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design 2001: 128-133
14		Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly: Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design 2001: 403-
	2000
13		Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara: Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD 2000: 550-556
12		Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya: Isomorph-Redundancy in Sequential Circuits. IEEE Trans. Computers 49(9): 992-997 (2000)
11		Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya: Synthesis of symmetric functions for path-delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1076-1081 (2000)
	1999
10		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC 1999: 287-
9		Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268
8		Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya: Synthesis of Symmetric Functions for Path-Delay Fault Testability. VLSI Design 1999: 512-517
	1998
7		Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya: Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. ASP-DAC 1998: 469-474
6		Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya: Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. VLSI Design 1998: 205-
	1997
5		Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya: New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. VLSI Design 1997: 303-309
	1996
4		Debesh Kumar Das, Bhargab B. Bhattacharya: Does retiming affect redundancy in sequential circuits? VLSI Design 1996: 260-263
3		Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya: Isomorph-redundancy in sequential circuits. VTS 1996: 463-469
	1995
2		Debesh K. Das, Bhargab B. Bhattacharya: Testable design of non-scan sequential circuits using extra logic. Asian Test Symposium 1995: 176-
	1993
1		Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya: Logical redundancies in irredundant combinational circuits. J. Electronic Testing 4(2): 125-130 (1993)

Coauthor Index

1	Bhargab B. Bhattacharya	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12] [15] [18] [20] [21] [24] [26] [32] [33] [34] [35] [36] [37]
2	Uttam K. Bhattacharya	[3] [12]
3	Vamsi Boppana	[17]
4	Susanta Chakrabarti	[11]
5	Susanta Chakraborty	[1] [5] [7] [8] [25]
6	Indrajit Chaudhuri	[6]
7	Parimal Pal Chaudhuri	[14] [17]
8	Sandip Das	[8] [11]
9	Sukanta Das	[29]
10	Hideo Fujiwara	[9] [13] [15] [22] [23] [25]
11	Niloy Ganguly	[14] [29]
12	Tomoo Inoue	[13] [25]
13	Dipak K. Kole	[34] [36] [37]
14	Yungang Li	[23]
15	Purnabha Majumder	[14]
16	Takahiro Mihara	[13]
17	Yinghua Min	[23]
18	Monalisa Mukherjee	[14] [19]
19	Sobhan Mukherjee	[17]
20	Satoshi Ohtake	[9] [15] [22]
21	Hafizur Rahaman	[10] [18] [20] [21] [24] [26] [27] [31] [32] [33] [34] [35] [36] [37]
22	Samir Roy	[16] [19] [28] [29] [30]
23	Chiiho Sano	[13]
24	Arijit Sarkar	[30]
25	Biplab K. Sikdar (Biplab Kumar Sikdar)	[14] [16] [17] [19] [28] [29] [30]
26	Shiyi Xu	[23]
27	Cliff Yang	[17]
28	Yervant Zorian	[23]

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