Carlos Dangelo

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1998

2 Carlos Dangelo: Design Productivity: How To Measure It, How To Improve It (Panel). DAC 1998: 578-579

1992

1 Vijay Nagasamy, Neerav Berry, Carlos Dangelo: Specification, Planning, and Synthesis in a VHDL Design Environment. IEEE Design & Test of Computers 9(2): 58-68 (1992)

	1998
2		Carlos Dangelo: Design Productivity: How To Measure It, How To Improve It (Panel). DAC 1998: 578-579
	1992
1		Vijay Nagasamy, Neerav Berry, Carlos Dangelo: Specification, Planning, and Synthesis in a VHDL Design Environment. IEEE Design & Test of Computers 9(2): 58-68 (1992)

Coauthor Index

1 Neerav Berry [1]

2 Vijay Nagasamy [1]

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —

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