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| 2009 | ||
|---|---|---|
| 3 | Yalei Cui, Zibin Dai: The Research of NULL Convention Logic Circuit Computing Model Targeted at Block Cipher Processing. IAS 2009: 552-555 | |
| 2008 | ||
| 2 | Zibin Dai, Wei Li, Xiaohui Yang, Tao Chen, Qiao Ren: The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing. ICESS 2008: 587-594 | |
| 2007 | ||
| 1 | Wei Li, Zibin Dai, Tao Chen, Tao Meng, Xuan Yang: Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit. APPT 2007: 50-59 | |
| 1 | Tao Chen | [1] [2] |
| 2 | Yalei Cui | [3] |
| 3 | Wei Li | [1] [2] |
| 4 | Tao Meng | [1] |
| 5 | Qiao Ren | [2] |
| 6 | Xiaohui Yang | [2] |
| 7 | Xuan Yang | [1] |
Colors in the list of coauthors
Last update Tue May 29 01:28:40 2012 CET by the DBLP Team —
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