Vinay Dabholkar

	1998
4		Vinay Dabholkar, Sreejit Chakravarty: Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391
3		Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy: Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998)
	1997
2		Vinay Dabholkar, Sreejit Chakravarty: Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148
	1995
1		Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel: Cyclic stress tests for full scan circuits. VTS 1995: 89-94

Coauthor Index

1	Sreejit Chakravarty	[1] [2] [3] [4]
2	J. Najm	[1]
3	Janak H. Patel	[1]
4	Irith Pomeranz	[3]
5	Sudhakar M. Reddy	[3]

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