 | 2009 |
|---|
| 8 |       | Oscar Alvarado Nava,
Arturo Díaz-Pérez:
Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology.
ReConFig 2009: 167-171 |
| 2005 |
|---|
| 7 | | Emmanuel López-Trejo,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
An FPGA Implementation of CCM Mode Using AES.
ICISC 2005: 322-334 |
| 6 | | Nazar A. Saqib,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
A reconfigurable processor for high speed point multiplication in elliptic curves.
IJES 1(3/4): 237-249 (2005) |
| 2004 |
|---|
| 5 | | Nazar A. Saqib,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2^m).
IPDPS 2004 |
| 4 | | Nazar A. Saqib,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
A Parallel Architecture for Computing Scalar Multiplication on Hessian Elliptic Curves.
ITCC (2) 2004: 493-497 |
| 3 | | Francisco Rodríguez-Henríquez,
Nazar A. Saqib,
Arturo Díaz-Pérez:
A fast parallel implementation of elliptic curve point multiplication over GF(2m).
Microprocessors and Microsystems 28(5-6): 329-339 (2004) |
| 2003 |
|---|
| 2 | | Nazar A. Saqib,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
AES Algorithm Implementation-An efficient approach for Sequential and Pipeline Architectures.
ENC 2003: 126-130 |
| 1 | | Nazar A. Saqib,
Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez:
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.
FPL 2003: 303-312 |
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