Hailong Cui

	2007
5		Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov: Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. ISQED 2007: 717-722
4		Michael Laisne, Triphuong Nguyen, Song-lin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman: Verification and debugging of IDDQ test of low power chips. ITC 2007: 1-7
3		Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov: Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. VLSI Design 2007: 805-812
	2003
2		Hailong Cui, Sharad C. Seth, Shashank K. Mehta: Modeling Fault Coverage of Random Test Patterns. J. Electronic Testing 19(3): 271-284 (2003)
	2002
1		Hailong Cui, Sharad C. Seth, Shashank K. Mehta: A Novel Method to Improve the Test Efficiency of VLSI Tests. VLSI Design 2002: 499-504

Coauthor Index

1	Rajsekhar Adapa	[3] [5]
2	Neetu Agrawal	[4]
3	Cher Bai	[4]
4	Edward Flanigan	[3] [5]
5	Michael Laisne	[3] [4] [5]
6	Shashank K. Mehta	[1] [2]
7	Triphuong Nguyen	[4]
8	Xiangdong Pan	[4]
9	M. Parley	[4]
10	Tsvetomir Petrov	[3] [5]
11	Sharad C. Seth	[1] [2]
12	A. Street	[4]
13	K. Sundararaman	[4]
14	Spyros Tragoudas	[3] [5]
15	Song-lin Zuo	[4]

Colors in the list of coauthors

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