 | 2011 |
|---|
| 9 |       | Aijiao Cui,
Chip-Hong Chang,
Li Zhang:
A hybrid watermarking scheme for sequential functions.
ISCAS 2011: 2333-2336 |
| 8 | | Aijiao Cui,
Chip-Hong Chang,
Sofiène Tahar,
Amr T. Abdel-Hamid:
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 678-690 (2011) |
| 2010 |
|---|
| 7 | | Chip-Hong Chang,
Aijiao Cui:
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property.
IEEE Trans. on Circuits and Systems 57-I(7): 1618-1630 (2010) |
| 2009 |
|---|
| 6 | | Aijiao Cui,
Chip-Hong Chang:
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering.
ISCAS 2009: 29-32 |
| 2008 |
|---|
| 5 | | Aijiao Cui,
Chip-Hong Chang:
Intellectual property authentication by watermarking scan chain in design-for-testability flow.
ISCAS 2008: 2645-2648 |
| 4 | | Aijiao Cui,
Chip-Hong Chang,
Sofiène Tahar:
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1565-1570 (2008) |
| 2007 |
|---|
| 3 | | Aijiao Cui,
Chip-Hong Chang:
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level.
ISCAS 2007: 3687-3690 |
| 2006 |
|---|
| 2 | | Aijiao Cui,
Chip-Hong Chang:
Kernel Extraction for Watermarking Combinational Logic Networks.
APCCAS 2006: 1023-1026 |
| 1 | | Aijiao Cui,
Chip-Hong Chang:
Stego-signature at logic synthesis level for digital design IP protection.
ISCAS 2006 |
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